Methods and apparatuses for depositing silicon nitride using a hybrid atomic layer deposition technique are provided. Methods and apparatuses for forming halogen-free undercoats in a process chamber using a halogen-free aminosilane precursor are provided. Methods and apparatuses for forming silicon oxynitride using a single-wafer chamber are provided herein. Methods and apparatus also include forming graded silicon oxynitride using cyclic deposition and in-situ nitridation and/or oxidation techniques.

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

A fabrication method, includes: forming a gate spacer layer around a sacrificial gate structure disposed over a substrate; performing, on a first material layer that includes the gate spacer layer, treatment operations that are configured to make the first material layer more resistant to Germanium (Ge) diffusion during metal gate replacement operations; forming a second material layer adjacent to the first material layer; and replacing the sacrificial gate structure with a metal gate, wherein the first material layer blocks Ge from entering the metal gate.

There is provided a technique that includes: (a) supplying a silicon- and ligand-containing gas to a substrate having a surface on a first base and second base are exposed to adsorb silicon contained in the silicon- and ligand-containing gas on a surface of one of the first and second base; (b) supplying a fluorine-containing gas to the substrate after the silicon is absorbed, to cause the silicon to react with the fluorine-containing gas to modify the surface to be F-terminated; and (c) supplying a film-forming gas to the substrate after the surface is modified, to thereby form a film on a surface of the other of the first base and the second base, which is different from the one of the first base and the second base.

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.

The present disclosure relates to an apparatus for injecting a gas, an apparatus for processing a substrate, and a method for depositing a thin-film, and more specifically, to an apparatus for injecting a gas to deposit a thin-film by injecting a gas to a substrate, an apparatus for processing a substrate, and a method for depositing a thin-film. An apparatus for injecting a gas in accordance with an exemplary embodiment includes: a first electrode in which a first gas supply path and a second gas supply path are separately defined and which has first and second gas supply holes connected to the first and second gas supply paths, respectively; and a second electrode which is electrically insulated from and spaced apart from the first electrode and has a plurality of openings arranged alternately with the first and second supply holes.

Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.

An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

A semiconductor structure includes: a semiconductor substrate; a gate dielectric layer over the semiconductor substrate; and a gate electrode over the gate dielectric layer. The gate dielectric layer includes a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion includes a third portion including nitrogen and enclosed by the first portion.