A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

A method of fabricating a pixel array substrate includes forming a semiconductor layer on a substrate, forming a metal layer stack on the semiconductor layer, forming a photoresist pattern on the metal layer stack, and removing part of the metal layer stack and the semiconductor layer not covered by the photoresist pattern at one time using a dry etching process to form a source, a drain, and a semiconductor pattern of an active device. The metal layer stack includes a first titanium layer, an aluminum layer, and a second titanium layer. The semiconductor pattern has a groove located between the source and the drain. The source and the drain respectively have a source edge and a drain edge opposite to each other, which defines two opposite side walls of the groove respectively. A pixel array substrate produced by using the method of fabricating the pixel array substrate is also disclosed.

The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

A method of processing a silicon surface includes using a first radical species to remove contamination from the surface and to roughen the surface; and using a second radical species to smooth the roughened surface. Reaction systems for performing such a method, and silicon surfaces prepared using such a method, also are provided.

A silicon wafer is provided in which a dopant is phosphorus, resistivity is from 0.5 m.Math.cm to 1.2 m.Math.cm, and carbon concentration is 3.010.sup.16 atoms/cm.sup.3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

A semiconductor device structure and a formation method are provided. The method includes forming multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner on a substrate. The method also includes partially removing the sacrificial layers and the semiconductor layers to form a recess exposing side edges of the sacrificial layers and the semiconductor layers. The method further includes forming p-type doped epitaxial structures on the side edges of the semiconductor layers and forming a germanium-containing epitaxial structure wrapped around the p-type doped epitaxial structures. The germanium-containing epitaxial structure has a higher atomic concentration of germanium than that of the p-type doped epitaxial structures. In addition, the method includes removing the sacrificial layers to release multiple semiconductor nanostructures constructed by remaining portions of the semiconductor layers and forming a metal gate stack wrapped around each of the semiconductor nanostructures.

A reaction apparatus for depositing an epitaxial layer on a semiconductor structure. The reaction apparatus includes a first gas inlet for channeling a first process gas into the reaction chamber in a first direction. The reaction apparatus includes a second gas inlet for channeling a second process gas into the reaction chamber in a second direction. The first direction and second direction form an angle of between 45 and 75.

There are provided (a) heat-treating a substrate including a film containing a group 14 element at a first temperature; (b) heat-treating the substrate at a second temperature higher than the first temperature; and (c) exposing the substrate to a treatment agent containing at least one of O and H after performing (a) and before performing (b).