Silicon wafer and epitaxial silicon wafer

Abstract

A silicon wafer is provided in which a dopant is phosphorus, resistivity is from 0.5 m.Math.cm to 1.2 m.Math.cm, and carbon concentration is 3.010.sup.16 atoms/cm.sup.3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

Claims

1. An epitaxial wafer of 200 mm in diameter comprising: a silicon substrate having a resistivity of 1.2 m-cm or less; an epitaxial layer on the silicon substrate; and a boundary between the epitaxial layer and the silicon substrate; wherein the silicon substrate has a carbon concentration of 3.010.sup.16 atoms/cm.sup.3 or more at about a center of the silicon substrate in a depth direction; and wherein one of the following three conditions is satisfied: (i) a carbon concentration in a region of the silicon substrate between the boundary and a position about 5 m from the boundary is decreased by 10% or more compared with the carbon concentration at about the center of the silicon substrate in the depth direction, or (ii) wherein a carbon concentration in a region of the silicon substrate between the boundary and a position about 8 m from the boundary is decreased by 10% or more compared with the carbon concentration at about the center of the silicon substrate in the depth direction, or (iii) wherein a carbon concentration in a region of the silicon substrate between the boundary and a position about 15 m from the boundary is decreased by 10% or more compared with the carbon concentration at about the center of the silicon substrate in the depth direction.

2. The epitaxial wafer of claim 1 wherein the carbon concentration is in a range of 3.010.sup.16 atoms/cm.sup.3 to 5.010.sup.17 atoms/cm.sup.3.

3. The epitaxial wafer of claim 1 wherein a top surface of the epitaxial layer contains 100 or fewer light point defects (LPDs) of 0.09 m or more in size.

4. The epitaxial wafer of claim 1 wherein a top surface of the epitaxial layer contains 60 or fewer LPDs of 0.09 m or more in size.

5. The epitaxial wafer of claim 1 further comprising an oxygen concentration in the silicon substrate in a range of 4.010.sup.17 atoms/cm.sup.3 to 1010.sup.17 atoms/cm.sup.3.

6. The epitaxial wafer of claim 1 wherein the resistivity of the silicon substrate is in a range of 0.5 m-cm to 1.2 m-cm.

7. The epitaxial wafer of claim 1 wherein the silicon substrate is substantially free of crystal-originated particles.

8. An epitaxial wafer of 200 mm in diameter comprising: a silicon substrate having a resistivity of 1.2 m-cm or less, and a carbon concentration of 3.010.sup.16 atoms/cm.sup.3 or more at about a center of the silicon substrate in a depth direction; an epitaxial layer on the silicon substrate; and a boundary between the epitaxial layer and the silicon substrate; wherein the silicon substrate further has a low carbon concentration layer near the boundary; and wherein one of the following three conditions is satisfied: (i) the low carbon concentration layer in the silicon substrate is within about 5 m of the boundary, and a carbon concentration in the low carbon concentration layer is decreased by 10% or more compared with the carbon concentration at about the center of the silicon substrate in the depth direction, or (ii) the low carbon concentration layer in the silicon substrate is within about 8 m of the boundary, and a carbon concentration in the low carbon concentration layer is decreased by 10% or more compared with the carbon concentration at about the center of the silicon substrate in the depth direction, or (iii) the low carbon concentration layer in the silicon substrate is within about 15 m of the boundary, and a carbon concentration in the low carbon concentration layer is decreased by 10% or more compared with the carbon concentration at about the center of the silicon substrate in the depth direction.

9. The epitaxial wafer of claim 8 wherein the carbon concentration is in a range of 3.010.sup.16 atoms/cm.sup.3 to 5.010.sup.17 atoms/cm.sup.3.

10. The epitaxial wafer of claim 8 wherein a top surface of the epitaxial layer contains 100 or fewer light point defects (LPDs) of 0.09 m or more in size.

11. The epitaxial wafer of claim 8 wherein a top surface of the epitaxial layer contains 60 or fewer LPDs of 0.09 m or more in size.

12. The epitaxial wafer of claim 8 further comprising an oxygen concentration in the silicon substrate in a range of 4.010.sup.17 atoms/cm.sup.3 to 1010.sup.17 atoms/cm.sup.3.

13. The epitaxial wafer of claim 8 wherein the resistivity of the silicon substrate is in a range of 0.5 m-cm to 1.2 m-cm.

14. The epitaxial wafer of claim 8 wherein the silicon substrate is substantially free of crystal-originated particles.

15. A silicon wafer having a diameter of 200 mm, a resistivity of 1.2 m-cm or less, and a carbon concentration of 3.01016 atoms/cm.sup.3 or more at about a center of the silicon wafer in a depth direction; wherein the silicon wafer has a top surface, and at least one of the following three conditions are satisfied: (i) a carbon concentration in a region of the silicon wafer between the top surface and a position about 5 m from the top surface is decreased by 10% or more compared with the carbon concentration at about the center of the silicon wafer in the depth direction, or (ii) a carbon concentration in a region of the silicon wafer between the top surface and a position about 8 m from the top surface is decreased by 10% or more compared with the carbon concentration at about the center of the silicon wafer in the depth direction, or (iii) a carbon concentration in a region of the silicon wafer between the top surface and a position about 15 m from the top surface is decreased by 10% or more compared with the carbon concentration at about the center of the silicon wafer in the depth direction.

16. The silicon wafer of claim 15 wherein the carbon concentration is in a range of 3.010.sup.16 atoms/cm.sup.3 to 5.010.sup.17 atoms/cm.sup.3.

17. The silicon wafer of claim 15 further comprising an oxygen concentration in a range of 4.010.sup.17 atoms/cm.sup.3 to 1010.sup.17 atoms/cm.sup.3.

18. The silicon wafer of claim 15 wherein the resistivity of the silicon wafer is in a range of 0.5 m-cm to 1.2 m-cm.

19. The silicon wafer of claim 15 wherein the silicon wafer is substantially free of crystal-originated particles.

20. An epitaxial wafer of 200 mm in diameter comprising: a silicon substrate having a resistivity of 1.2 m-cm or less; an epitaxial layer on top of the silicon substrate; and a boundary between the epitaxial layer and the silicon substrate; wherein a carbon concentration in the silicon substrate is 3.010.sup.16 atoms/cm.sup.3 or more at about a center of the silicon substrate in a depth direction, and a carbon concentration in a region of the silicon substrate between the boundary and a position about 5 m to 15 m from the boundary is decreased by 10% or more compared with the carbon concentration at about the center of the silicon substrate in the depth direction.

21. The epitaxial wafer of claim 20 wherein the carbon concentration is in a range of 3.010.sup.16 atoms/cm.sup.3 to 5.010.sup.17 atoms/cm.sup.3.

22. The epitaxial wafer of claim 20 wherein a top surface of the epitaxial layer has 100 or less LPDs of 0.09 m or more in size.

23. The epitaxial wafer of claim 20 further comprising an oxygen concentration in the silicon substrate in a range of 4.010.sup.17 atoms/cm.sup.3 to 1010.sup.17 atoms/cm.sup.3.

24. The epitaxial wafer of claim 20 wherein the silicon substrate has a top surface and a bottom surface and the resistivity of 1.2 m-cm or less is measured from either the top surface or the bottom surface.

25. A silicon wafer of 200 mm in diameter doped with phosphorus and having a resistivity of 1.2 m-cm or less, the silicon wafer comprising a top surface and a bottom surface; wherein a carbon concentration in the silicon wafer is 3.010.sup.16 atoms/cm.sup.3 or more at about a center of the silicon wafer in a depth direction, and a carbon concentration in a region of the silicon wafer between the top surface and a position about 5 m to 15 m from the top surface is decreased by 10% or more compared with the carbon concentration at about the center of the silicon wafer in the depth direction.

26. The silicon wafer of claim 25 wherein the carbon concentration is in a range of 3.010.sup.16 atoms/cm.sup.3 to 5.010.sup.17 atoms/cm.sup.3.

27. The silicon wafer of claim 25 further comprising an oxygen concentration in a range of 4.010.sup.17 atoms/cm.sup.3 to 1010.sup.17 atoms/cm.sup.3.

28. The silicon wafer of claim 25 wherein the resistivity of 1.2 m-cm or less is measured from either the top surface or the bottom surface.

29. A method of making an epitaxial wafer of 200 mm in diameter, comprising: placing a crucible in a furnace; adding phosphorus and carbon to a silicon melt in the crucible; rotationally pulling a single crystal from the silicon melt with a puller; cutting the single crystal to form at least one silicon wafer; heating the silicon wafer at a temperature between 1150 C. to 1250 C. in an atmosphere charged with argon gas for a duration between 30 to 120 minutes; and forming an epitaxial layer on a surface of the silicon wafer, wherein the silicon wafer has a carbon concentration of 3.010.sup.16 atoms/cm.sup.3 or more at about a center of the silicon wafer in a depth direction therein, and wherein one of the following three conditions is satisfied: (i) a carbon concentration in a region of the silicon wafer between a boundary between the silicon wafer and the epitaxial layer and a position about 5 m from the boundary is decreased by 10% or more compared with the carbon concentration at about the center of the silicon wafer in the depth direction, or (ii) a carbon concentration in a region of the silicon wafer between the boundary and a position about 8 m from the boundary is decreased by 10% or more compared with the carbon concentration at about the center of the silicon wafer in the depth direction, or (iii) a carbon concentration in a region of the silicon wafer between the boundary and a position about 15 m from the boundary is decreased by 10% or more compared with the carbon concentration at about the center of the silicon wafer in the depth direction.

30. The method of claim 29 further comprising applying magnetic field to the silicon melt and controlling pressure in the furnace so that the silicon wafer has an oxygen concentration between 4.010.sup.17 atoms/cm.sup.3 to 1010.sup.17 atoms/cm.sup.3.

31. The method of claim 30 wherein the oxygen concentration is measured from about halfway in the depth direction of the silicon wafer.

32. The method of claim 29 wherein the silicon wafer has a resistivity of 1.2 m.Math.cm or less.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention is further described in the detailed description that follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention, in which like reference numerals represent similar parts throughout the several views of the drawings, and wherein:

(2) FIGS. 1A and 1B are photographs of a compound dislocation loop that is observed in a silicon wafer that is cut from a crystal region with a long residence time in an SF nucleation temperature zone;

(3) FIG. 2 is a photograph of a dislocation loop that is observed in a silicon wafer that is cut from a crystal region with a short residence time in an SF nucleation temperature zone;

(4) FIG. 3 is a flow chart illustrating an embodiment of a method for manufacturing an epitaxial silicon wafer according to the present invention;

(5) FIGS. 4A and 4B are cross-sectional views of the embodiment of the epitaxial silicon wafer according to the present invention;

(6) FIGS. 5A and 5B are graphs illustrating evaluation results for dislocation loops in the epitaxial silicon wafers of Example 1 and Comparative Example 1;

(7) FIG. 6 is a graph illustrating research findings for a carbon concentration profile of the epitaxial silicon wafers of Examples 4 and 5;

(8) FIGS. 7A to 7D are X-ray topography images of the surface of silicon wafers of Examples 6 and 7 and Comparative Examples 4 and 5; and

(9) FIG. 8 is a graph illustrating a relationship between LPD density and resistivity when the epitaxial layer is formed on the surface of the respective silicon wafer in Examples 8 and 9 and Comparative Examples 6 and 7.

DETAILED DESCRIPTION OF THE INVENTION

(10) The particulars shown herein are by way of example and for purposes of illustrative discussion of the embodiments of the present invention only and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the present invention. In this regard, no attempt is made to show structural details of the present invention in more detail than is necessary for the fundamental understanding of the present invention, the description taken with the drawings making apparent to those skilled in the art how the forms of the present invention may be embodied in practice.

(11) Hereafter, an embodiment of the present invention is described with reference to the drawings. A silicon wafer according to the present invention is 200 mm in diameter, is doped with phosphorus, which is a dopant for resistivity adjustment, has resistivity of 0.5 m.Math.cm or more and 1.2 m.Math.cm or less, and has a carbon concentration of 3.010.sup.16 atoms/cm.sup.3 or more. The silicon wafer having a diameter of 200 mm that is defined by the present invention means a silicon wafer having a diameter of 2000.5 mm due to a machining error and the like. In addition, an epitaxial silicon wafer according to the present invention includes a silicon epitaxial layer that is on the silicon wafer.

(12) A favorable manufacturing flow for obtaining an epitaxial silicon wafer according to the present invention is shown in FIG. 3. The manufacturing flow preferably includes a step of manufacturing a single crystal ingot (S1), a step of forming an oxide film on a back side (S2), a step of removing the oxide film at an outer periphery (S3), a step of argon annealing (S4), a step of prebaking (S5), and a step of forming an epitaxial layer (S6).

(13) In the single crystal ingot manufacturing step S1, according to the Czochralski (CZ) method, which uses a single crystal ingot pulling apparatus (not shown), a 200 mm-diameter single crystal silicon ingot doped with phosphorus as an n-type dopant is manufactured satisfying the following conditions.

(14) Phosphorus Concentration

(15) By doping red phosphorus such that the phosphorus concentration in the single crystal ingot is 6.010.sup.19 atoms/cm.sup.3 or more and 1.6410.sup.20 atoms/cm.sup.3 or less, a single crystal ingot with resistivity of 0.5 m.Math.cm or more and 1.2 m.Math.cm or less can be obtained. In addition, by configuring the phosphorus concentration to be 8.310.sup.19 atoms/cm.sup.3 or more, a single crystal ingot with resistivity of 0.9 m.Math.cm or less can be obtained. The phosphorus concentration of the silicon wafer is a value obtained by measuring the phosphorus concentration about the center of the silicon wafer in the depth direction using SIMS. The phosphorus concentration can be found from the resistivity measured by the four-point probe method using a formula or a graph prescribed by SEMI MF723-0307. When phosphorus is doped prior to melting a silicon raw material, phosphorus may evaporate during the melting of the silicon raw material and a desired resistivity cannot be obtained. Therefore, it is preferred to dope red phosphorus into the silicon melt after the silicon raw material is melted.

(16) Carbon Concentration

(17) By adding carbon powder to the crucible with the silicon raw material and melting the material such that the carbon concentration in the single crystal ingot is 3.010.sup.16 atoms/cm.sup.3 or more and 5.010.sup.17 atoms/cm.sup.3 or less, s single crystal ingot having a predetermined carbon concentration can be grown. By setting the carbon concentration to be 3.010.sup.16 atoms/cm.sup.3 or more, a dislocation loop defect that forms inside the silicon wafer can be reduced in size and density and SF density generated in the epitaxial layer after the epitaxial growth process can be significantly reduced. Specifically, even with a silicon wafer cut from the top side of a crystal with a long residence time in an SF nucleation temperature zone, the wafer functions as a silicon wafer that reliably allows LPD density on the surface of the silicon epitaxial layer after the epitaxial growth process to be 100 defects/wafer or less.

(18) Although the effect of reducing the LPD density (SF density) that is generated in the epitaxial layer is enhanced as the carbon concentration increases, when the carbon concentration exceeds 5.010.sup.17 atoms/cm.sup.3, dislocation becomes more likely to occur in the single crystal during the process of growing the single crystal ingot, which makes it difficult to grow the single crystal ingot with no dislocations. From a viewpoint of stabilizing manufacture of single crystal ingots, the carbon concentration is more preferably 3.010.sup.17 atoms/cm.sup.3 or less.

(19) Oxygen Concentration

(20) When the oxygen concentration of the silicon wafer is high, device pressure resisting characteristics tend to be deteriorated, as noted below, and therefore it is preferable to keep the oxygen concentration in the single crystal ingot low, and the oxygen concentration is preferably in a range of 4.010.sup.17 atoms/cm.sup.3 or more and 1010.sup.17 atoms/cm.sup.3 or less.

(21) In order to grow a single crystal ingot with low oxygen concentration, it is preferably to apply a magnetic field to the silicon melt, and a well-known horizontal magnetic field or cusp magnetic field may be applied. The oxygen concentration incorporated into the single crystal can be reduced to the desired concentration by slowing down the rotation of a crucible that stores the silicon melt and by lowering the furnace pressure of the pulling apparatus, and the like. When the oxygen concentration is less than 4.010.sup.17 atoms/cm.sup.3, the silicon wafer has low strength and slip dislocation may occur when the silicon wafer undergoes high-temperature heat treatment. Therefore, the oxygen concentration is preferably 4.010.sup.17 atoms/cm.sup.3 or more.

(22) After this, a silicon wafer is cut from s single crystal ingot that is manufactured using the single crystal ingot manufacturing step S1 and a predetermined process (such as grinding, etching, and polishing processes) is performed to create a mirror surface silicon wafer with excellent surface roughness and flatness.

(23) In the backside oxide film formation step S2, preferably the oxide film (hereafter referred to as the backside oxide film) is formed on the backside of the silicon wafer using a CVD device under the following condition ranges.

(24) Raw material gas: mixed gas of monosilane (SiH.sub.4) and oxygen (O.sub.2)

(25) Thickness of the backside oxide film: from 100 nm to 1500 nm

(26) Film formation temperature: from 400 C. to 450 C.

(27) Providing a backside oxide film of this type can inhibit auto-doping and can inhibit resistance fluctuation in the epitaxial layer.

(28) In the backside oxide film formation step S2, it is difficult to form the oxide film only on the backside of the silicon wafer, and an oxide film forming on the end portion (chamfered portion) of the silicon wafer after the backside oxide film formation step S2 may be unavoidable. When the epitaxial layer is formed on the surface of the oxide film, nodules (granular silicon) may appear in the area, so it is preferable to remove the oxide film that is formed at the outer periphery of the backside and the end portion of the silicon wafer.

(29) Accordingly, in the outer periphery oxide film removal step S3, with the use of various methods such as polishing and etching, the oxide film present on the end portion (chamfered portion) of the silicon wafer and the outer periphery of the wafer backside may be removed. The oxide film present on the outer periphery of the wafer backside is preferably removed over an area less than 5 mm from an outer edge of the silicon wafer. By removing the outer periphery of the backside oxide film and the end portion of the silicon wafer in this way, the occurrence of nodules during the growth of the silicon epitaxial layer can be prevented and the occurrence of particles from the wafer edge can be prevented.

(30) In the argon annealing step S4, heat treatment is preferably performed under the following condition ranges. Gas atmosphere: argon gas Heat treatment temperature: from 1150 C. to 1250 C. Heat treatment time: from 30 to 120 min
A batch furnace (vertical heat treatment device) capable of heat-treating a plurality of silicon wafers at once is preferably used as a heat treatment device to perform the heat treatment.

(31) With highly concentrated carbon doping, the generation of a large dislocation loop defect in the silicon wafer is inhibited and small dislocation loop defects present on the silicon wafer can be eliminated by performing argon annealing on the silicon wafer, and the generation of SF in the epitaxial layer can be reduced as much as possible.

(32) In addition, by performing argon annealing on the silicon wafer prior to the epitaxial growth process, carbon diffusion to the silicon epitaxial layer from the silicon wafer that is generated during the epitaxial layer formation step S6 can be reduced. This point is described below. FIG. 4A is a schematic view illustrating a low carbon concentration layer formed on a surface layer of the silicon wafer by argon annealing. As shown in FIG. 4A, by performing high-temperature argon annealing on a silicon wafer 11, carbon in the surface layer of the silicon wafer 11 outwardly diffuses and the carbon concentration of the surface layer is reduced. Thereby, a low carbon concentration layer 12 is formed on a front and backside of the silicon wafer 11, the low carbon concentration layer 12 having a lower carbon concentration than the carbon concentration about the center C of the silicon wafer 11 where carbon outward diffusion does not occur.

(33) FIG. 4B is a schematic view illustrating a carbon concentration profile when the epitaxial growth process is performed on the silicon wafer subjected to argon annealing. As shown in FIG. 4B, the carbon concentration after the epitaxial layer formation step S6 shows a concentration profile where the carbon concentration in the surface layer of the silicon wafer is reduced. Here, when a region is defined as the low carbon concentration layer 12, the region having a carbon concentration that is 0.9 times or less that of the center C of the silicon wafer 11 where carbon outward diffusion does not occur, after the epitaxial growth process, a depth D of the low carbon concentration layer 12 formed on a surface side of the silicon wafer 11 that is in contact with the silicon epitaxial layer 13 can be 5 m or more and 15 m or less. That is to say, the carbon concentration is decreased by 10% or more starting from a depth in the silicon substrate of about 5 m from the boundary, compared with the carbon concentration at about the center, in the depth direction, of the silicon wafer. In another embodiment, the carbon concentration is decreased by 10% or more starting from a depth in the silicon substrate of anywhere from 5 m to 15 m from the boundary, compared with the carbon concentration at about the center, in the depth direction, of the silicon wafer. With formation of the low carbon concentration layer 12, carbon diffusion to the silicon epitaxial layer 13 from the silicon wafer 11 that is generated during the epitaxial layer formation step S6 can further be reduced. The thickness of the low carbon concentration layer 12 can be adjusted as desired by adjusting time and heat treatment temperature of the argon annealing.

(34) In the prebaking step S5 under an atmosphere of gas that includes hydrogen and hydrogen chloride, a heat treatment is preferably performed on the silicon wafer under the following condition ranges in an internal epitaxial device (CENTURA, manufactured by Applied Materials, Inc.). Atmosphere: hydrogen gas, hydrogen chloride gas Hydrogen gas flow: 40 L/min Hydrogen chloride gas flow: 1 L/min Heat treatment temperature: from 1150 C. to 1250 C. Heat treatment time: from 30 to 300 seconds

(35) The margin of the surface layer of the silicon wafer resulting from the prebaking step S5 is preferably 100 nm to 300 nm, and more preferably 150 nm10 nm.

(36) In the epitaxial layer formation step S6, an epitaxial layer is preferably grown under the following condition ranges on the silicon wafer that has undergone the prebaking step S5. Dopant gas: phosphine (PH.sub.3) gas Material source gas: trichlorosilane (SiHCl.sub.3) gas Carrier gas: hydrogen gas Growth temperature: from 1050 C. to 1150 C. Thickness of epitaxial layer: from 1 m to 10 m Epitaxial layer resistivity: from 0.01 m.Math.cm to 10 m.Math.cm Phosphorus concentration: from 4.4410.sup.14 atoms/cm.sup.3 to 4.5310.sup.18 atoms/cm.sup.3
By performing the epitaxial layer formation step S6, the epitaxial silicon wafer where the silicon epitaxial layer is formed on the surface of the silicon wafer is manufactured.

(37) By performing the process flow noted above, it is possible to provide a silicon wafer that can reduce the generation of SF in the epitaxial layer, and to provide an epitaxial silicon wafer where the SF density in the epitaxial layer is reduced. Specifically, a new silicon wafer that not previously existed is provided, where the silicon wafer is 200 mm in diameter, phosphorus is added such that the resistivity is from 0.5 m.Math.cm to 1.2 m.Math.cm, and the silicon wafer is densely doped with carbon such that the carbon concentration is 3.010.sup.16 atoms/cm.sup.3 or more.

(38) Through highly concentrated carbon doping, the density of large dislocation loop defects in the silicon wafer is reduced. The silicon wafer functions effectively as a bulk wafer for epitaxial growth that can reduce the generation of epitaxial defects (LPD or SF observed on the surface of the epitaxial layer).

(39) Moreover, by configuring the oxygen concentration of the silicon wafer to be in a range from 4.010.sup.17 atoms/cm.sup.3 to 1010.sup.17 atoms/cm.sup.3, when carbon is doped, poor device pressure resistance can be prevented.

(40) In addition, by performing argon annealing on the silicon wafer before forming the silicon epitaxial layer, the carbon concentration in the surface layer of the silicon wafer is reduced and an amount of carbon diffusion to the silicon epitaxial layer that is generated during the silicon epitaxial layer formation can be reduced. By reducing the amount of carbon diffusion to the silicon epitaxial layer, at the time of heat treatment in a device process where a device is fabricated on the epitaxial silicon wafer, deterioration of electric characteristics due to the generation of a defect caused by carbon incorporated in the silicon epitaxial layer can be inhibited.

(41) In the above-noted embodiment, the resistivity of the silicon wafer is from 0.5 m.Math.cm to 1.2 m.Math.cm. However, as the silicon wafer with better resistivity, preferably the resistivity is from 0.5 m.Math.cm to 0.9 m.Math.cm. The lower the resistivity is, the more noticeable the generation of SF in the epitaxial layer becomes, and therefore the effect of carbon doping according to the present invention is more apparent.

(42) Further, the silicon wafer according to the present embodiment is manufactured from the single crystal ingot grown from the silicon melt that is doped with phosphorus such that the resistivity is 1.2 m.Math.cm or less. Because phosphorus is densely added, an oxidation-induced stacking fault (OSF) ring region where OSF is generated in the process of manufacturing the single crystal ingot is eliminated, centering around the ingot, and becomes a crystal region with no COPs. In other words, the silicon wafer according to the present embodiment can be configured as a silicon wafer with no COPs by densely adding phosphorus and the generation of defects caused by COPs in the epitaxial layer can be prevented.

EXAMPLES

(43) Hereafter, experimental conditions and evaluation results of examples and comparative examples of the present invention are described.

(44) <Dislocation Loop Evaluation>

(45) Dislocation loops are evaluated for the following Example 1 and Comparative Example 1.

Example 1

(46) In Example 1, an epitaxial silicon wafer is manufactured under the condition ranges of the manufacturing flow of the epitaxial silicon wafer described with reference to FIG. 3. The growth conditions of the single crystal ingot are to manufacture a single crystal ingot by adding carbon powder before melting a silicon raw material and by adding phosphorus into the silicon melt after the silicon raw material is melted such that the resistivity on a top end of a straight body of the single crystal ingot is 0.9 m.Math.cm. A sample wafer is cut from the position of the ingot on the top side of the straight body of the single crystal ingot to which the carbon was added, and a mirror surface silicon wafer is manufactured by performing predetermined processing. The resistivity of the silicon wafer is 0.75 m.Math.cm when measured by the four-point probe method and the carbon concentration of the silicon wafer is 5.010.sup.16 atoms/cm.sup.3.

Comparative Example 1

(47) Compared to Example 1 above, the silicon wafer is manufactured under the same manufacturing conditions as Example 1, except that carbon doping is not performed at the stage of growing the single crystal ingot. Similar to Example 1, a sample wafer with resistivity of 0.75 m.Math.cm is cut and a mirror surface silicon wafer is produced by performing the predetermined processing.

(48) The silicon wafers of Example 1 and Comparative Example 1 are cleaved in the depth direction and the cleavage cross section is observed by a Transmission Electron Microscope (TEM). FIGS. 5A and 5B are graphs illustrating evaluation results for dislocation loops in the silicon wafers of Example 1 and Comparative Example 1. In FIGS. 5A and 5B, the horizontal axis represents dislocation loop size and the vertical axis represents dislocation loop density. FIG. 5A shows the results for the silicon wafer of Comparative Example 1, which is not doped with carbon, and since the sample wafer that is cut from the top side of the crystal with the long residence time in the SF nucleation temperature zone is used, a large number of large dislocation loops that exceed 60 nm in size were observed. On the other hand, FIG. 5B shows the results for the silicon wafer of Example 1, which is densely doped with carbon, and since the sample wafer that is cut from the top side of the crystal with the long residence time in the SF nucleation temperature zone is used, the density of large dislocation loops that exceed 60 nm is found to be significantly lowered, although a large number of small dislocation loops are observed. In other words, the density of large dislocation loops that are formed in the silicon wafer is found to be reduced by carbon doping.

(49) [LPD Density Evaluation]

(50) When a silicon epitaxial layer is formed using a sample silicon wafer cut from the top side of the straight body of an ingot with a long residence time in the temperature zone where SF nuclei are formed, the SF is frequently generated in the epitaxial layer and the LPD density is increased, and therefore, in the present example, a sample silicon wafer for Examples 2 and 3 and Comparative Examples 2 and 3 below that is cut from the top side of the straight body is produced and the LPD density that is observed on the surface of the epitaxial layer after the epitaxial layer formation is measured.

(51) Specific conditions for the backside oxide film formation step and the epitaxial layer formation step, which are performed as a common treatment in both the Examples and Comparative Examples, are as follows.

(52) [Backside Oxide Film Formation Conditions]

(53) A backside oxide film is formed on the backside of each silicon wafer (opposite surface from the surface where the epitaxial layer is formed) under the following conditions. Raw material gas: mixed gas of monosilane (SiH.sub.4) and oxygen (O.sub.2) Film formation method: CVD method Film formation temperature: 400 C. Thickness of the backside oxide film: 550 nm

(54) The oxide film present on the chamfered portion and the outer periphery of the backside of each silicon wafer is removed by an etching process.

(55) [Hydrogen Baking Treatment Conditions]

(56) Atmosphere: hydrogen gas Heat treatment temperature: 1200 C. Heat treatment time: 30 seconds
[Epitaxial Film Growth Conditions] Dopant gas: phosphine (PH.sub.3) gas Material source gas: trichlorosilane (SiHCl.sub.3) gas Carrier gas: hydrogen gas Growth temperature: 1080 C. Thickness of epitaxial layer: 4 m Resistivity (epitaxial film resistivity): 0.3 .Math.cm

Comparative Example 2

(57) An epitaxial silicon wafer is manufactured without performing carbon doping, by forming a silicon epitaxial layer with 4 m thickness on the surface of the silicon wafer of Comparative Example 1 in which a large number of dislocation loops are observed.

Comparative Example 3

(58) After performing argon annealing (heat treatment at 1200 C. for 30 min under an argon gas atmosphere) on the silicon wafer of Comparative Example 1, an epitaxial silicon wafer is manufactured by forming a silicon epitaxial layer with 4 m thickness on the surface of the silicon wafer.

Example 2

(59) An epitaxial silicon wafer is manufactured without performing argon annealing on the silicon wafer of Example 1, in which carbon doping was performed, by forming a silicon epitaxial layer with 4 m thickness on the surface of the silicon wafer.

Example 3

(60) After performing argon annealing (heat treatment for 1200 C.30 min under the argon gas atmosphere) to the silicon wafer in Example 1, the epitaxial silicon wafer is manufactured by forming the silicon epitaxial layer with 4 m thickness on the surface of silicon wafer. Conditions for epitaxial growth process are the same for Examples 2, 3 and Comparative Examples 2, 3.

(61) The LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer of Comparative Example 2 is measured using a surface defect inspection device (SURFSCAN SP-1 manufactured by KLA-Tencor Corporation). Specifically, measurement is performed in Normal mode (DCN mode) and a density of LPD that are 90 nm or more in size observed on the surface of the epitaxial layer is measured. The measurement area is the surface of the epitaxial layer excluding the annular region from the circumferential edge of the epitaxial silicon wafer to 3 mm from the circumferential edge in the radial direction. The number of counted LPD can be considered as a number of SF. As a result, the measurement of LPD itself cannot be performed because of overflow (100,000 defects/wafer or more) due to the detected number being too large. In Comparative Example 3, in which argon annealing is performed on the silicon wafer, although the LPD density can be reduced compared to Comparative Example 2, 235 LPD/wafer are observed. The following LPD density measurements for each example and each comparison are performed under the same conditions as in Comparative Example 2.

(62) When the LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer in Example 2 is measured, 90,000 LPD/wafer or more are observed. This is presumed to be due to a large number of small dislocation loops less than 60 nm in size being presented, although the density of large compound dislocation loops in the silicon wafer is reduced by carbon doping.

(63) In Example 3, in which argon annealing is performed on the silicon wafer prior to the epitaxial growth process, the LPD density on the surface of the epitaxial layer is significantly reduced and an LPD density of 56 defects/wafer is observed. This is considered to be due to small dislocation loops less than 60 nm in size that are present in the surface layer of the silicon wafer being removed by argon annealing.

(64) Given the above, when carbon is doped and argon annealing is performed to the silicon wafer, the effect of reducing the generation of SF in the silicon epitaxial layer is enhanced and it is clear that the LPD density after the epitaxial layer formation can be reduced to about one-fourth compared to Comparative Example 3.

(65) [Carbon Concentration Profile Evaluation]

(66) When carbon is densely doped, due to the heat treatment during the formation of the silicon epitaxial layer, carbon diffusion to the silicon epitaxial layer may occur, and therefore, behavior of carbon diffusion to the silicon epitaxial wafer is evaluated.

Example 4

(67) A silicon wafer with high carbon concentration (carbon concentration about the center of the wafer in the depth direction: 6.510.sup.16 atoms/cm.sup.3) is prepared and an epitaxial silicon wafer is manufactured in which a silicon epitaxial layer similar to Example 2 is formed without performing argon annealing.

Example 5

(68) After performing the same argon annealing as in Example 3 on a silicon wafer similar to that of Example 4, an epitaxial silicon wafer is manufactured in which a silicon epitaxial layer is formed.

(69) FIG. 6 is a graph illustrating research findings for a carbon concentration profile measured by secondary ion mass spectrometry for the epitaxial silicon wafers of Examples 4 and 5. The horizontal axis in FIG. 6 represents a depth from the surface of the epitaxial silicon wafer and the vertical axis represents carbon concentration. There is an interface between the silicon epitaxial layer and the silicon wafer at a depth of 4 m from the surface of the epitaxial silicon wafer.

(70) In Example 4, in which argon annealing is not performed on the silicon wafer, the width of the low carbon concentration layer is less than 1 m. That is, the carbon concentration is decreased at a depth within 1 m from the surface of the silicon wafer, compared to the carbon concentration near the center depth of the silicon wafer. On the other hand, in Example 5, in which argon annealing is performed before forming the silicon epitaxial layer, a low carbon concentration layer having 8.2 m thickness is formed in the depth direction of the wafer from the interface between the silicon epitaxial layer and silicon wafer, and it was found that the carbon concentration of the silicon epitaxial layer covers almost the entire epitaxial layer except for the vicinity of the interface with the silicon wafer, and the carbon concentration is a detection limit or less (2.010.sup.15 atoms/cm.sup.3 or less). That is, the carbon concentration is decreased at a depth within 8.2 m from the surface of the silicon wafer, compared with the carbon concentration near the center depth of the silicon wafer. The thickness of the low carbon concentration layer depends on the argon annealing conditions. For example, all other conditions are set similar to those in Example 5, and when heat treatment conditions are changed to 1150 C. for 10 min, the thickness is 5.6 m, 7.3 m when heat treatment conditions are changed to 1200 C. for 10 min, 7.3 m when heat treatment conditions are changed to 1150 C. for 60 min, and 9.4 m when heat treatment conditions are changed to 1200 C. for 60 min. In other words, the thickness of the low carbon concentration layer can be adjusted as desired by adjusting the heat treatment temperature and time for argon annealing. By forming a low carbon concentration layer of a predetermined thickness on the surface layer of the silicon wafer, the amount of carbon diffusion to the epitaxial layer from the silicon wafer can be reduced.

(71) [Slip Dislocation Evaluation]

(72) For the following Comparative Examples 4 and 5 and Examples 6 and 7, studies are performed as to whether slip dislocation (defect along a silicon crystal surface) occurs based on whether carbon doping or argon annealing were performed. Specifications and conditions shared by Comparative Examples 4 and 5 and Examples 6 and 7 are listed below. Resistivity: 0.82 m.Math.cm Carbon concentration: 4.010.sup.16 atoms/cm.sup.3

(73) In addition, the argon annealing of Comparative Example 5 and Example 7 where argon annealing is performed is a heat treatment at 1200 C. for 30 min under an argon gas atmosphere. Further, in the following descriptions, heat treatment that corresponds to epitaxial layer growth conditions is a heat treatment that is performed without material source gas being introduced inside the epitaxial device (CENTURA, manufactured by Applied Materials, Inc.) and means a heat treatment at 1150 C. for 10 min under a hydrogen gas atmosphere.

Comparative Example 4

(74) A heat treatment that corresponds to the epitaxial layer growth conditions is performed without performing argon annealing on the silicon wafer that is not doped with carbon (the heat treatment alone does not cause the silicon epitaxial layer to grow).

Comparative Example 5

(75) Argon annealing is performed on a silicon wafer that is not doped with carbon, and a heat treatment that corresponds to the epitaxial layer growth conditions is performed.

Example 6

(76) A heat treatment that corresponds to the epitaxial layer growth conditions is performed without performing argon annealing on a silicon wafer that is doped with carbon.

Example 7

(77) Argon annealing is performed on a silicon wafer that is doped with carbon, and a heat treatment that corresponds to the epitaxial layer growth conditions is performed.

(78) For each silicon wafer, presence of a slip dislocation observed on the wafer surface is checked by X-ray topography. As a result, as shown in FIG. 7, no slip dislocation was found in any of the silicon wafers and it was also found that slip dislocation does not occur even when a silicon wafer is densely doped with carbon.

(79) [Verification of Resistivity, Carbon Concentration, and LPD Density]

(80) For the following Comparative Examples 6 and 7 and Examples 8 and 9, in order to verify correlations between resistivity, carbon concentration, and LPD density, silicon wafers are manufactured under various conditions, an epitaxial layer is formed on the surface of each silicon wafer, and the LPD density observed on the surface of the epitaxial layers is measured. Moreover, the argon annealing of Comparative Example 7 and Example 9 below is a heat treatment at 1200 C. for 30 min under an argon gas atmosphere.

Comparative Example 6

(81) Without performing carbon doping, phosphorus is doped such that the resistivity on the top end of the straight body of a single crystal ingot is 1.2 m.Math.cm and the single crystal ingot is grown with a resistivity range from 0.5 m.Math.cm to 1.2 m.Math.cm, and a plurality of silicon wafers with different resistivity are manufactured from the single crystal ingot. A silicon epitaxial layer with 4 m thickness is formed without performing argon annealing on any of the silicon wafers.

Comparative Example 7

(82) Similar to Comparative Example 6, carbon doping is not performed and a single crystal ingot is grown with a resistivity range from 0.5 m.Math.cm to 1.2 m.Math.cm, and a plurality of silicon wafers with different resistivity are manufactured from the single crystal ingot. Without performing carbon doping, an epitaxial layer with 4 m thickness is formed after argon annealing is performed on each of the silicon wafers.

Example 8

(83) Similar to Comparative Example 6, a single crystal ingot with a resistivity range from 0.5 m.Math.cm to 1.2 m.Math.cm is grown, and a plurality of silicon wafers with different resistivity were manufactured from the single crystal ingot. Carbon doping is performed such that the carbon concentration on the top end of the straight body of the single crystal ingot is 3.010.sup.16 atoms/cm.sup.3, however an epitaxial layer with 4 m thickness is formed without performing argon annealing on any of the silicon wafers.

Example 9

(84) Similar to Comparative Example 6, a single crystal ingot with a resistivity range from 0.5 m.Math.cm to 1.2 m.Math.cm is grown, and a plurality of silicon wafers with different resistivity were manufactured from the single crystal ingot. Carbon doping is performed such that the carbon concentration on the top end of the straight body of the single crystal ingot is 3.010.sup.16 atoms/cm.sup.3, and an epitaxial layer with 4 m thickness is formed after performing argon annealing on each of the silicon wafers.

(85) FIG. 8 is a graph for the epitaxial layer in Examples 8 and 9 and Comparative Examples 6 and 7 illustrating a relationship between the resistivity of a silicon wafer and the LPD density observed on the surface of an epitaxial layer. The horizontal axis in FIG. 8 shows, using a solidification rate of the straight body of an ingot, a position where the silicon wafer is cut when a solidification amount of the entire length of the straight body of the grown ingot is set as 1.

(86) As shown in FIG. 8, in Example 8 in which carbon doping is performed and argon annealing is not performed prior to the epitaxial growth process, an LPD density of approximately 5,000 defects/wafer is observed in a silicon wafer that is cut from a position on the straight body of the ingot near the solidification rate of 0.1, which is the crystal region on the top side, confirming an effect of reducing the LPD density. However, the LPD density overflowed in a silicon wafer that is cut from a position on the straight body of the ingot near the solidification rate of 0.3. In addition, when the silicon wafer that is cut from a crystal region on a bottom side is used, the LPD density can be reduced to 150 defects/wafer or less even with a silicon wafer having an extreme resistivity of 0.5 m.Math.cm.

(87) In Example 9, where carbon doping is performed and argon annealing is performed prior to the epitaxial growth process, the LPD density can be reduced to 60 defects/wafer or less even when a silicon wafer that is cut from the crystal region on the top side is used. This is due to refinement of dislocation loop defects achieved with highly concentrated carbon doping and due to eliminating refined dislocation loop defects by performing argon annealing on the silicon wafer, and the effect of reducing SF through a synergistic effect of highly concentrated carbon doping and argon annealing was found to be extremely significant. On the other hand, when a silicon wafer is used that is cut from the crystal region on the bottom side (where the solidification rate is 0.6 or more), which has a short residence time in an SF nucleation temperature zone, the LPD density can be reduced to a total of 10 defects/wafer or less.

(88) On the other hand, in Comparative Example 6, where carbon doping is not performed and argon annealing is not performed on the silicon wafer, when a silicon wafer that is cut from the crystal region on the top side is used, the LPD density overflows, and although the LPD density is significantly reduced when a silicon wafer that is cut from the crystal region on the bottom side is used, the LPD density is 100 defects/wafer or more for a silicon wafer having resistivity of 0.5 m.Math.cm. Further, in Comparative Example 7, where carbon doping is not performed and argon annealing is performed on the silicon wafer prior to the epitaxial growth process, the LPD density can be reduced compared to Comparative Example 6. However, when a silicon wafer that is cut from the crystal region on the top side is used, the LPD density is from 100 defects/wafer to 300 defects/wafer.

(89) Based on the above-noted results, by performing carbon doping of 3.010.sup.16 atoms/cm.sup.3 or more and by performing argon annealing on the silicon wafer prior to the epitaxial growth process, the LPD density observed on the surface of the epitaxial layer in all crystal regions of the single crystal ingot can be reduced to at least 100 defects/wafer. In addition, even when argon annealing is not performed on the silicon wafer, by performing carbon doping, the LPD density can be reduced to 100 defects/wafer or less in the crystal region on the bottom side. Although the present examples do not disclose all experimental examples that were developed, the inventors of the present invention found that, when highly concentrated carbon of at least 3.010.sup.16 atoms/cm.sup.3 or more is added, the LPD density after the epitaxial growth process can be reduced for a silicon wafer having resistivity from 0.5 m.Math.cm to 1.2 m.Math.cm as compared to a case where carbon is not added.

(90) [Evaluation of Device Pressure Resisting Characteristics]

(91) Device pressure resisting characteristics are evaluated. In this example, the device pressure resistance is one of the quality characteristics of a semiconductor device and means the voltage when a breakdown occurs by gradually increasing the voltage between a drain and a source in a state where a path between a gate and a source that configure the semiconductor device is short circuited.

(92) When oxygen in the silicon wafer diffuses into the epitaxial layer where the semiconductor device is fabricated, there is a concern that the device pressure resisting characteristics may be affected. Because of this, the inventors of the present invention prepared silicon wafers with six different levels of oxygen concentration, formed a silicon epitaxial layer on each silicon wafer, and studied whether there is a difference in the device pressure resisting characteristics based on the difference in oxygen concentration. Further, studies were made as to whether there is a difference in the device pressure resisting characteristics based on whether the silicon wafer was doped with carbon.

(93) Specifically, the semiconductor device is fabricated on each of the epitaxial silicon wafers in samples 1 to 12 in Table 1, a predetermined voltage is applied between the drain and source in a state where the path between the gate and the source that configure the semiconductor device is short circuited, and the pressure resisting characteristics were determined to be poor when breakdown occurred whereas the pressure resisting characteristics were determined to be good when breakdown did not occur.

(94) The epitaxial silicon wafer in samples 1 to 6 is 200 mm in diameter, has had phosphorus added, and has a silicon epitaxial layer with 4 m thickness formed on the silicon wafer having resistivity of 0.75 m.Math.cm, and is a sample wafer where the epitaxial layer is formed on each of the silicon wafers having six different levels of oxygen concentration and no carbon added. The epitaxial silicon wafer in samples 7-12 is, similar to samples 1 to 6, 200 mm in diameter, has had phosphorus added, and has a silicon epitaxial layer with 4 m thickness formed on the silicon wafer having resistivity of 0.75 m.Math.cm, and is a sample wafer where the carbon concentration is 6.010.sup.16 atoms/cm.sup.3 and the epitaxial layer is formed on each of the silicon wafers having six different levels of oxygen concentration. The carbon concentration and oxygen concentration are each a value obtained by thinning the silicon wafer by polishing, and then measuring the concentration about the center of the silicon wafer in the depth direction using SIMS.

(95) TABLE-US-00001 TABLE 1 Epitaxial Carbon Oxygen Pressure silicon concentration concentration resisting wafer (atoms/cm.sup.3) (atoms/cm.sup.3) characteristics Sample 1 Detection limit or less 18 10.sup.17 Poor Sample 2 Detection limit or less 15 10.sup.17 Good Sample 3 Detection limit or less 13 10.sup.17 Good Sample 4 Detection limit or less 10 10.sup.17 Good Sample 5 Detection limit or less 8.0 10.sup.17 Good Sample 6 Detection limit or less 4 10.sup.17 Good Sample 7 6.0 10.sup.16 18 10.sup.17 Poor Sample 8 6.0 10.sup.16 15 10.sup.17 Poor Sample 9 6.0 10.sup.16 13 10.sup.17 Poor Sample 10 6.0 10.sup.16 10 10.sup.17 Good Sample 11 6.0 10.sup.16 8.0 10.sup.17 Good Sample 12 6.0 10.sup.16 4.0 10.sup.17 Good

(96) As shown in Table 1, device pressure resistance in samples 7-9 is confirmed to likely be poor when carbon doping is performed. However, even when carbon doping is performed, it is confirmed that poor device pressure resistance can be prevented by configuring the oxygen concentration to 1010.sup.17 atoms/cm.sup.3 or less.

(97) It is noted that the foregoing examples have been provided merely for the purpose of explanation and are in no way to be construed as limiting of the present invention. While the present invention has been described with reference to exemplary embodiments, it is understood that the words that have been used herein are words of description and illustration, rather than words of limitation. Changes may be made, within the purview of the appended claims, as presently stated and as amended, without departing from the scope and spirit of the present invention in its aspects. Although the present invention has been described herein with reference to particular structures, materials and embodiments, the present invention is not intended to be limited to the particulars disclosed herein; rather, the present invention extends to all functionally equivalent structures, methods and uses, such as are within the scope of the appended claims.

(98) The present invention is not limited to the above described embodiments, and various variations and modifications may be possible without departing from the scope of the present invention.