A silicon carbide power device has: a die having a functional layer of silicon carbide and an edge area and an active area, surrounded by the edge area; gate structures formed on a top surface of the functional layer in the active area; and a gate contact pad for biasing the gate structures. The device also has an integrated resistor having a doped region, of a first conductivity type, arranged at the front surface of the functional layer in the edge area; wherein the integrated resistor defines an insulated resistance in the functional layer, interposed between the gate structures and the gate contact pad.

A silicon carbide device includes: a planar gate structure on a first surface of a silicon carbide substrate, the planar gate structure having a gate length along a lateral first direction; a source region of a first conductivity type extending under the planar gate structure over at least part of the gate length; a body region of a second conductivity type, the body region including a channel zone that adjoins the source region under the planar gate structure; and a shielding region of the second conductivity type covering the channel zone over at least 20% but less than 100% of the gate length, wherein a maximum dopant concentration in the shielding region is higher than a maximum dopant concentration in the body region.

An apparatus is provided. The apparatus includes a disk configured to rotate during an ion implantation process. The apparatus includes a wafer support assembly coupled to the disk and configured to support one or more semiconductor wafers. The rotation of the disk causes the one or more semiconductor wafers to revolve along a path. The apparatus includes an ion implanter configured to emit an ion beam to a beam position along the path. The apparatus includes a vibration calibration device including a calibration base coupled to the disk and a first calibration unit coupled to the calibration base. The vibration calibration device is configured to move the first calibration unit from a first position to a second position to reduce a vibration associated with the apparatus.

Semiconductor devices and methods are provided. An exemplary method includes forming a first fin and a second fin, each of the first fin and the second fin comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, forming a first gate stack and a second gate stack over the first fin and the second fin, respectively, the first gate stack and the second gate stack having different gate lengths, forming a first source/drain feature adjacent to the first gate stack and a second source/drain feature adjacent to the second gate stack, after forming the second source/drain feature, performing an ion implantation process to increase a dopant concentration of an upper portion of the second source/drain feature.

A power device and a method for manufacturing the power device are provided. The power device includes an electrical substrate, an epitaxial layer, a well region, a plurality of doping regions, a plurality of trenches, a first oxidation layer, a second oxidation layer, a polycrystalline silicon filler, two shielding regions, a dielectric layer, and a metallic electrically conductive layer.

Provided is an amorphous silicon thin-film transistor including an amorphous silicon semiconductor layer, a source electrode, and a drain electrode that are successively disposed on a base substrate. Ions doped by an ion implantation process are present in a region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer. A concentration of the ions in a surface region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer is greater than or equal to 5*10{circumflex over ()}20 atoms/cc.

In a mesa region sandwiched between adjacent active trenches among mesa regions that are regions each sandwiched between adjacent trenches, a third semiconductor layer has regions discretely arranged in a first direction so as to be in contact with one active trench of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction so as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched between the adjacent active trenches, a fourth semiconductor layer is disposed between the third semiconductor layer on the side in contact with the one active trench and the third semiconductor layer on the side in contact with the other active trench in plan view and between the respective regions of the third semiconductor layer discrete in the first direction.

Methods for fabricating SiC MOSFETs using compensating ion implants are disclosed. An n-type silicon carbide layer is epitaxially grown. After this growth process, a compensating ion implantation process is performed. This ion implantation process is used to compensate for the known dopant non-uniformity in the n-type silicon carbide layer. After the dopant concentration has been compensated, the traditional processes used to fabricate a planar SiC MOSFET may be performed. For super junction MOSFETs, the n-type epitaxial growth and compensating ion implantation processes may be repeated a plurality of times.

Disclosed are a semiconductor device based on seedless silicon (Si) source/drain contact resistance reduction and laser process technology and a method of fabricating the same. The semiconductor device includes an activated seedless Si layer formed on a substrate and at least one electrode formed on the seedless Si layer, and the seedless Si layer is crystalized through a first laser process and then activated through a second laser process.

A transistor device includes a substrate, a source region provided on the substrate, a drain region in the substrate, spaced apart from the source region in a direction parallel to a top surface of the substrate, a gate electrode provided on the substrate and between the source region and the drain region, a gate insulating film interposed between the gate electrode and the substrate, and a constant current generating layer extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, wherein the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.