A semiconductor structure includes a substrate, at least one first fin protruded from the substrate, and a 3D capacitor disposed over the substrate. The 3D capacitor includes a doped electrode conformally disposed in the first fin, a metal electrode disposed over the doped electrode, and a dielectric layer disposed between the doped electrode and the metal electrode.

A bipolar transistor includes a sub-collector doped with a first dopant type and situated in a semiconductor substrate, a device layer doped with the first dopant type situated over the sub-collector, and a shallow trench isolation (STI) situated in the device layer and bordering a collector of the bipolar transistor. The bipolar transistor further includes a Reduced Surface Layer (RESURF) region doped with a second dopant type opposite the first dopant type situated between the collector and the STI, wherein the RESURF region protects against breakdown of the bipolar transistor.

A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.

A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.

A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm.sup.3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.

A base layer has a low concentration peak at a position between a portion located at a same depth as a lower end portion of a gate electrode and a portion located at a same depth as an upper end portion of the gate electrode in a concentration profile of an impurity concentration in a depth direction. An impurity region has a boundary with the base layer in the depth direction at a position between a first peak position, at which the impurity concentration of the base layer is maximum between the portion located at the same depth as the lower end portion and the position of the low concentration peak, and a second peak position, at which the impurity concentration of the base layer is maximum between the position of the low concentration peak and the portion located at the same depth as the upper end portion.

A semiconductor device includes: a semiconductor substrate having an active device region that includes a plurality of device cells and a termination region between the active device region and an edge of the semiconductor substrate; a field termination structure in the termination region and including a continuous region of a first conductivity type and a plurality of rings of the first conductivity type in the continuous region and having a higher average doping concentration than the continuous region; and a charge balance structure in the active device region and including interleaved columns of the first conductivity type and of a second conductivity type opposite the first conductivity type. The charge balance structure extends into the termination region below the field termination structure such that at least an outermost one of the columns of the first conductivity type is connected to the continuous region of the field termination structure.

A method for manufacturing a semiconductor device according to an embodiment includes forming a first mask material having a first opening on a surface of a silicon carbide layer, performing first ion implantation of forming a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask, forming, on the surface of the silicon carbide layer, a second mask material in which both end portions in a first direction parallel to the surface have second openings disposed inside both end portions in the first direction of the first carbon region, performing second ion implantation of forming a first impurity region by implanting a first impurity into the silicon carbide layer using the second mask material as a mask, and performing heat treatment at 1600 C. or higher.

The method includes performing a well implantation process to dope a dopant into a semiconductor substrate; after performing the well implantation process, performing a flash anneal on the semiconductor substrate, the flash anneal including a first preheat step and a first annealing step after the first preheat step, the first preheat step performed at a preheat temperature ranging from about 200 C. to about 800 C., the first annealing step having a peak temperature ramp profile, the peak temperature ramp profile having a peak temperature ranging from about 1000 C. to about 1200 C.; after performing the flash anneal, performing a rapid thermal anneal (RTA) on the semiconductor substrate, the RTA including a second preheat step, the first preheat step of the flash anneal being performed for a shorter duration than the second preheat step of the RTA.