A method of forming a semiconductor package includes providing a metal lead frame comprising a die pad and a plurality of leads, mounting a high-voltage die on an upper surface of the die pad such that a load terminal of the high-voltage die is electrically connected to the die pad, mounting an electrical isolation pad on the die pad, and mounting a low-voltage die on the electrical isolation pad, wherein at least one of: mounting the high-voltage die, mounting the electrical isolation pad, and mounting the low-voltage die includes performing a float-limiting attachment process, wherein the float-limiting attachment process comprises performing a surface roughening process to an attachment surface that forms a border of roughened surface around a mounting area, arranging an attachment material within the mounting area with a mounting element disposed thereon, and liquifying the attachment material with the mounting element disposed thereon.

A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

A low-inductance power module comprises a housing, upper-bridge MOSs, lower-bridge SBDs, lower-bridge MOSs, upper-bridge SBDs, output electrodes, a positive electrode and a negative electrode. A bottom plate is mounted inside the housing. An insulating substrate is mounted at the top of the bottom plate. A positive-electrode copper layer, a negative-electrode copper layer and an output-electrode copper layer are arranged on the upper surface of the insulating substrate. The output-electrode copper layer is divided into an upper-side output-electrode copper layer and a lower-side output-electrode copper layer.

Implementations of a leadframe may include a substrate attach portion including a first largest planar surface and a second largest planar surface on a side opposing the first largest planar surface; and a substrate opening formed in a material of the first largest planar surface of the substrate attach portion. The substrate opening may be configured to receive a perimeter of a substrate therein.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.

In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode, a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode; a first terminal provided on the semiconductor package, the first terminal being electrically connected to the first electrode; a plurality of second terminals provided on the semiconductor package, the second terminals being electrically connected to the first electrode, and the second terminals being lined up in a first direction; a third terminal provided on the semiconductor package, the third terminal being electrically connected to the fourth electrode; a plurality of fourth terminals provided on the semiconductor package, the fourth terminals being electrically connected to the first control electrode; and a plurality of fifth terminals provided on the semiconductor package, the fifth terminals being electrically connected to the second control electrode, and the fifth terminals being lined up in the first direction.

A semiconductor device includes a chip carrier, a first power chip arranged above a mounting surface of the chip carrier, a laminate arranged above a top surface of the first power chip facing away from the chip carrier, and a first logic chip configured to drive the first power chip and arranged above a top surface of the laminate facing away from the chip carrier. The first power chip and the first logic chip are electrically coupled via an electrical wiring of the laminate.