H10P14/40

Photoelectric conversion element, photodetector, photodetection system, electronic apparatus, and mobile body

A highly functional photoelectric conversion element is provided. The photoelectric conversion element includes: a semiconductor substrate; a first photoelectric converter that is provided on the semiconductor substrate, and detects light in a first wavelength range and photoelectrically converts the light; a second photoelectric converter that is provided at a position overlapping the first photoelectric converter in a thickness direction of the semiconductor substrate in the semiconductor substrate, and detects light in a second wavelength range and photoelectrically converts the light; an optical filter that is sandwiched between the first photoelectric converter and the second photoelectric converter in the thickness direction, and through which the light in the second wavelength range passes more easily than the light in the first wavelength range; and a first light-shielding member that surrounds the optical filter along a plane orthogonal to the thickness direction to at least partially overlap the optical filter in a plane direction along the plane, and shields at least the light in the second wavelength range.

PALLADIUM COBALT OXIDE THIN FILM, DELAFOSSITE-TYPE OXIDE THIN FILM, SCHOTTKY ELECTRODE HAVING DELAFOSSITE-TYPE OXIDE THIN FILM, METHOD FOR PRODUCING PALLADIUM COBALT OXIDE THIN FILM, AND METHOD FOR PRODUCING DELAFOSSITE-TYPE OXIDE THIN FILM

A palladium cobalt oxide thin film, a delafossite-type oxide thin film, a Schottky electrode having a delafossite-type oxide thin film, a method for producing a palladium cobalt oxide thin film, and a method for producing a delafossite-type oxide thin film are provided. In the palladium cobalt oxide thin film, the crystal grain size in the film is 100 nm or more and 500 nm or less, the thickness is greater than the critical film thickness, and the roughness value in the thickness direction is 4 nm or less.

SOURCE/DRAIN CONTACT IN SINGLE DIFFUSION BREAK REGION
20260026070 · 2026-01-22 ·

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second transistor separated by a single diffusion break; and a source/drain contact to a source/drain region of the first transistor, the source/drain region being next to the single diffusion break, where the source/drain contact has an L-shape having a vertical portion on top of a horizontal portion, the horizontal portion extending at least partially into a sidewall spacer at a sidewall of the single diffusion break. A method of forming the same is also provided.

Bonding system

A first transfer device and a second transfer device are configured to transfer a first substrate and a second substrate in a normal pressure atmosphere. A third transfer device is configured to transfer the first substrate and the second substrate in a decompressed atmosphere. A load lock chamber has accommodation sections allowed to accommodate therein the first substrate and the second substrate, and is allowed to switch an inside of the accommodation sections between the normal pressure atmosphere and the decompressed atmosphere. Multiple gates are respectively disposed on three different sides of the load lock chamber, and allowed to open or close the load lock chamber. The first transfer device, the second transfer device, and the third transfer device carry the first substrate and the second substrate into/out of the load lock chamber through different gates among the multiple gates.

Bonding system

A first transfer device and a second transfer device are configured to transfer a first substrate and a second substrate in a normal pressure atmosphere. A third transfer device is configured to transfer the first substrate and the second substrate in a decompressed atmosphere. A load lock chamber has accommodation sections allowed to accommodate therein the first substrate and the second substrate, and is allowed to switch an inside of the accommodation sections between the normal pressure atmosphere and the decompressed atmosphere. Multiple gates are respectively disposed on three different sides of the load lock chamber, and allowed to open or close the load lock chamber. The first transfer device, the second transfer device, and the third transfer device carry the first substrate and the second substrate into/out of the load lock chamber through different gates among the multiple gates.

CONTACT STRUCTURE WITH LOW CONTACT RESISTANCE AND METHOD OF MANUFACTURING THE SAME

A contact with low contact resistance is provided in the present invention, including a dielectric layer on a substrate, a contact hole formed in the dielectric layer and exposing the substrate, an N-type or P-type metal oxide film on the surface of contact hole, a barrier layer on the metal oxide film, and a contact plug on the barrier layer and filling up the contact hole, wherein a 2DEG or 2DHG is formed in the substrate near the contact surface between the contact and the substrate.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC DEVICE

A semiconductor device, a manufacturing method, and an electronic device capable of achieving both formation of a capacitive element and reduction in parasitic capacitance. A semiconductor device includes an internal electrode on a first surface side of a semiconductor substrate, a through hole at a position corresponding to the internal electrode, a first rewiring on a second surface side of the semiconductor substrate and connected to the internal electrode via the through hole, a second rewiring connected to the first rewiring on a side closer to an external connection terminal than the first rewiring, and an interlayer insulating film between the first and second rewirings. Two of a first internal electrode and a second internal electrode are provided as the internal electrode, and the first rewiring connected to the first internal electrode, the second rewiring connected to the second internal electrode, and the interlayer insulating film constitute a capacitor.

Power switch circuit, IC structure of power switch circuit, and method of forming IC structure

An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first control signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

Etching method and plasma processing apparatus
12563979 · 2026-02-24 · ·

An etching method and a plasma processing apparatus form a recess with an intended shape. The etching method includes (a) providing a substrate, the substrate including a silicon-containing film and a mask on the silicon-containing film; (b) etching the silicon-containing film with a first plasma to form a recess, the first plasma generated from a first process gas; (c) supplying a second plasma to the substrate, the second plasma generated from a second process gas comprising tungsten; and (d) etching the recess with a third plasma generated from a third process gas.

PLASMA TREATMENT FOR DEPOSITION OF METALS
20260052914 · 2026-02-19 ·

In one example, a method for depositing ruthenium includes forming an opening in a dielectric layer disposed over a substrate, exposing the substrate including the opening to a first plasma in a plasma processing chamber including nitrogen and hydrogen, and exposing the substrate including the opening to a second plasma in the plasma processing chamber. The second plasma is hydrogen free. The method includes depositing ruthenium into the opening after exposing the substrate to the second ptext missing or illegible when filed