A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A method for etching a dielectric layer covering a top and a flank of a three-dimensional structure, this method including a first etching of the dielectric layer, including a first fluorine based compound, a second compound taken from SiwCl(2w+2) and SiwF(2w+2), oxygen, this first etching being carried out to form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and second etchings being repeated until removing the dielectric layer located on the flank of the structure. The second etching can be carried out by hydrogen-based plasma.

The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.

A substrate processing method includes the processes of preparing a substrate having a concave-convex structure, forming a dielectric film including at least silicon and nitrogen on the concavo-convex structure, to form the dielectric film having a non-uniform portion in a recess of the concavo-convex structure, and forming a protective film on a surface of the dielectric film by exposing the dielectric film to first plasma including an oxygen gas, to form the protective film including a cap layer that closes the non-uniform portion by bonding an upper side of the non-uniform portion of the concavo-convex structure.

Disclosed are methods and systems for depositing layers comprising a metal and nitrogen. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

Disclosed are methods and systems for depositing layers comprising a metal and nitrogen. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

In an embodiment, a method for nitriding a substrate is provided. The method includes flowing a nitrogen-containing source and a carrier gas into a plasma processing source coupled to a chamber such that a flow rate of the nitrogen-containing source is from about 3% to 20% of a flow rate of the carrier gas; generating an inductively-coupled plasma (ICP) in the plasma processing source by operating an ICP source, the ICP comprising a radical species formed from the nitrogen-containing source, the carrier gas, or both; and nitriding the substrate within the chamber, wherein nitriding includes operating a heat source within the chamber at a temperature from about 150 C. to about 650 C. to heat the substrate; maintaining a pressure of the chamber from about 50 mTorr to about 2 Torr; introducing the ICP to the chamber; and adjusting a characteristic of the substrate by exposing the substrate to the radical species.

A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50 C. to 100 C., and a duration of the baking process is between 5 seconds to 120 seconds.