A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a PAI process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers. By performing the above operations, dislocations are controllably and intentionally formed and carrier mobility in the number of channel layers may be advantageously enhanced, leading to improved device performance.

In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.

The present disclosure describes a semiconductor device with modulated gate structures and a method for forming the same. The method includes forming a fin structure, depositing a polysilicon layer over the fin structure, and forming a photoresist mask layer on the polysilicon layer. The method further includes etching, with a first etching condition, the polysilicon layer not covered by the photoresist mask layer and above a top surface of the fin structure. The method further includes etching, with a second etching condition, the polysilicon layer not covered by the photoresist mask layer and below the top surface of the fin structure, where the etched polysilicon layer below the top surface of the fin structure is narrower than the etched polysilicon layer above the top surface of the fin structure. The method further includes removing the etched polysilicon layer to form a space and forming a gate structure in the space.

A semiconductor device includes a fin on a substrate extending along a fin direction, a first and a second source/drain features on the fin. The semiconductor device also includes a stack of semiconductor layers over a first portion of the fin and between the first source/drain feature and the second source/drain feature. The semiconductor device further includes a gate structure over the stack of semiconductor layers. The gate structure extends along a gate direction perpendicular to the fin direction. Moreover, the gate structure engages with the stack of semiconductor layers. The semiconductor device includes a dielectric layer interposing between the first source/drain feature and the fin along a vertical direction, where the vertical direction is perpendicular to the fin direction and to the gate direction. The dielectric layer interfaces with the first portion of the fin and isolates the first source/drain feature from the first portion of the fin.

A process for producing nanoclusters of silicon and/or germanium exhibiting a permanent magnetic and/or electric dipole moment for adjusting the work function of materials, for micro- and nano-electronics, for telecommunications, for nano-ovens, for organic electronics, for photoelectric devices, for catalytic reactions and for fractionation of water.

A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.