Provided is a semiconductor device including: a first trench portion having a predetermined first trench length; a second trench portion having a second trench length longer than the first trench length; a first gate runner portion configured to be electrically connected to an end portion of the first trench portion; and a second gate runner portion configured to be electrically connected to the first gate runner portion and electrically connected to an end portion of the second trench portion. A resistivity per unit length of the first gate runner portion is larger than a resistivity per unit length of the second gate runner portion.

The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.

A nitride-based semiconductor circuit including a substrate structure, a nitride-based heterostructure, connectors, and connecting vias is provided. The substrate structure includes a first type semiconductor substrate, and a second type semiconductor substrate. The second type semiconductor substrate is embedded in a region of the first type semiconductor substrate. The first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate. The nitride-based heterostructure is disposed on the substrate structure. The connectors are disposed on the nitride-based heterostructure. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first region of the first type semiconductor substrate to one of the connectors. The second interconnection electrically connects the second type semiconductor substrate to another one of the connectors.

An MIM capacitor structure includes a dielectric layer. An MIM capacitor body is disposed on the dielectric layer. The MIM capacitor body includes a first electrode and a second electrode stacked alternately and a capacitor dielectric layer disposed between the first electrode and the second electrode. The first electrode has a first extension part extending out from the MIM capacitor body. The second electrode has a second extension part extending out from the MIM capacitor body. The first extension part includes a first aluminum-containing material layer. The second extension part includes a second aluminum-containing material layer. A first conductive plug penetrates the first extension part, wherein the first conductive plug has a first arc which is concave toward the first aluminum-containing material layer. A second conductive plug penetrates the second extension part, wherein the second conductive plug has a second arc which is concave toward the second aluminum-containing material layer.

A semiconductor structure includes a plurality of first wafers and a through-substrate via (TSV). The plurality of first wafers include a plurality of conductive connection lines. Each of the conductive connection lines is located in the corresponding first wafer. The through-substrate via passes through the plurality of first wafers and a plurality of end portions of the plurality of conductive connection lines. The plurality of end portions are embedded in the through-substrate via.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

A substrate, having edges, a device region, and at least one bonding region, includes a base, device groups, signal line groups, and conductive patterns. The device groups are along first and second directions. The signal line groups are on the same side as the device groups. A signal line group includes signal lines extending along the second direction, and arranged at intervals along the first direction. Any signal line extends from a bonding region to the device region, and is electrically connected to a column of device groups. The conductive patterns are on the same side as the device groups. At least one conductive pattern is in a region where a device group is located, and/or at least one conductive pattern is in a region between two adjacent device groups. At least one signal line in at least one signal line group is electrically connected to a conductive pattern.

An interconnect structure includes a plurality of first pads, a plurality of second pads, and a plurality of conductive lines. The first pads are arranged to form a first column-and-row array, and the second pads are arranged to form a second column-and-row array. The first column-and-row array, the second column-and-row array and the conductive lines are disposed in a same layer. The first pads in adjacent rows in the first column-and-row array are separated from each other by a first vertical distance from a plan view, the second pads in adjacent rows in the second column-and-row array are separated from each other by a second vertical distance from the plan view. A sum of widths of the conductive lines electrically connecting the first pads and the second pads in the same row is less than the first vertical distance and the second vertical distance from the plan view.

The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact and a drain contact are disposed within the active area. The drain contact is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure. The first plurality of conductive contacts are separated along the first direction by distances overlying the gate extension finger.