The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Semiconductor devices with die overthinning detection circuitry (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a semiconductor die includes a substrate, a triple well structure positioned at least partially within the substrate, and circuitry. The triple well structure can form a depletion region within the substrate, and the circuitry can be configured to capture a measurement of an amount of leakage current from the depletion region while a reverse bias is applied across the triple well structure. In some embodiments, the reverse bias can be applied across the triple well structure using part of a metallization die border of the semiconductor die. In these and other embodiments, measurement of the amount of leakage current can be used to detect that the semiconductor die is defective (e.g., overthinned, overpolished).

A semiconductor wafer comprising a first die including a first integrated circuit having a trimmable or programmable component. The trimmable or programmable component is configured to be trimmed or permanently altered in response to an electrical signal. The semiconductor wafer also includes a saw street arranged adjacent to the first die, and at least one probe pad electrically connected to the trimmable or programmable component. The at least one probe pad is arranged in the saw street.

A device includes a plurality of semiconductor chips, a device under test (DUT) circuit, a control circuit, and a switch circuit. The semiconductor chips are fabricated on a semiconductor wafer that includes one or more scribe lines. The DUT circuit is formed along at least one of the scribe lines and includes a plurality of DUTs. The switch circuit is connected between the DUT circuit and the control circuit. The control circuit generates a plurality of control signals. The switch circuit connects the DUTs to a test probe pad one at a time in response to the control signals. A method for verifying characteristics of the semiconductor chips is also disclosed.

A manufacturing method for a semiconductor device includes a preparation step of preparing a wafer that has a first surface on one side and a second surface on the other side, a first supporting step of supporting the wafer from the first surface side by a first member of a plate shape, a thinning step of thinning the wafer in a state where the wafer is supported by the first member, a second supporting step of supporting the wafer from a peripheral edge portion side of the second surface by a second member of a plate shape that exposes an inner portion of the second surface after the thinning step, and a removing step of removing the first member from the first surface side in a state where the wafer is supported by the second member.

Provided are a semiconductor package of which yield may be improved through rescuing and a test method and a rescue method for the semiconductor package. The semiconductor package includes a base chip, a plurality of memory chips stacked on the base chip, and a deactivation controller configured to deactivate the memory chips, wherein the memory chips are classified into at least two stack-ID (SID) regions, each of the at least two SID regions includes a subset of the plurality (set number) of memory chips, and, when a fail-SID region including a failed memory chip, from among the at least two SID regions, exists, the deactivation controller is configured to deactivate all memory chips included in the fail-SID region, and activate memory chips in remaining SID regions other than the fail-SID region.

A display device includes a circuit substrate, a first light-emitting diode (LED), a second LED, a repair LED, a first protective structure, and a second protective structure. The circuit substrate includes a first pixel region and a second pixel region. The first pixel region includes a first placement region and a first repair region, and the second pixel region includes a second placement region and a second repair region. The first LED and the second LED are respectively located on the first pixel region and the second pixel region. The repair LED is located on the first repair region. The first protective structure and the second protective structure are located on the first repair region and the second repair region respectively. The first protective structure is in contact with the repair LED.

A memory wafer is described. The memory wafer includes memory dies on the memory wafer. Additionally, the memory wafer includes wire connections at least partially within one of the memory dies. The wire connections are configured to couple to memory test and repair pads along at least one scribe line between the one of the memory dies and adjacent memory dies.

A heterogeneous integration testing structure is provided that includes a solder bridge that is configured for solder contact resistance measurement or solder sheet resistivity measurement. The heterogeneous integration testing structure is typically integrated in a far back-end of an integrated circuit containing structure. The solder bridge includes under ball metallurgy and solder that is formed over a plurality of electrical components located in the far back-end of the integrated circuit containing structure in which solder contact resistance measurement or solder sheet resistivity measurement is required.

A device comprising a substrate; and a stack of chips coupled to the substrate, wherein the stack of chips comprises: a logic chip; and a first memory chip coupled to the logic chip, wherein the first memory chip comprises a first die substrate; a first plurality of memory cells; and a first plurality of memory cell structures located along at least one edge of the first memory chip.