A probe card for testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having a trimmable or programmable component. The probe card including at least one probe arranged to make electrical contact with at least one probe pad arranged on the wafer. The at least one probe pad being electrically connected to the trimmable or programmable component and being arranged in a saw street of the wafer.

An apparatus includes a first glass plate, and an outer layer disposed over the first glass plate. The first glass plate and the outer layer are configured to hold a semiconductor die disposed on the first glass plate, and a solder preform interposed between the semiconductor die and the outer layer. The solder preform is viewable through the first glass plate.

This invention provides an asymmetric pads structure using at a scribe line of a wafer, comprising a test element device electrically connected to a first pad and a second pad separately, wherein a first spacing between the second pad and the test element device is sufficient to accommodate the second pad of an another asymmetric pads structure. So, two neighboring asymmetric pads structures may cross to each other to form a cross configuration.

A semiconductor structure includes vertical conductive features disposed over a substrate, and horizontal conductive features disposed over the vertical conductive features. The horizontal conductive features include first and second conductive lines respectively electrically connected to the first and second vertical conductive features, a first conductive segment disposed between the first vertical conductive feature and the second conductive line, and a second conductive segment disposed between the first conductive line and the second vertical conductive feature. The first conductive segment is electrically isolated from the vertical conductive features. The second conductive segment is electrically isolated from the vertical conductive features.

Provided is a semiconductor memory package including: a buffer semiconductor die including an interface circuit configured to perform communication with a memory controller; a plurality of core semiconductor dies stacked in a vertical direction on the buffer semiconductor die, wherein a core semiconductor die of the plurality of core semiconductor dies includes a semiconductor memory device; and a heterogeneous semiconductor die stacked with the buffer semiconductor die and the plurality of core semiconductor dies, wherein the heterogeneous semiconductor die includes: a capacitor array including a plurality of power capacitors; and an electrode conductor connecting electrodes of the plurality of power capacitors.

Test systems and methods testing semiconductor package structures including an improved socket housing plate design that provides improved testing reliability and accuracy. The upper surface of the socket housing plate includes a non-planar shape, such as a stepped configuration including a plurality of different regions having different vertical elevations. The non-planar shape of the upper surface of the socket housing plate may mimic the warpage characteristics of the semiconductor package structures being tested, which may enable improved contact between the semiconductor package structure and the contact pins of the test system. This may improve the accuracy of the testing and reduce the occurrence of false reject tests.

The present description concerns a detection device including a semiconductor region buried from a first surface of a semiconductor substrate of a first conductivity type, the buried semiconductor region being of a second conductivity type and being between a second surface of the semiconductor substrate and an electronic circuit, a first semiconductor region of the second conductivity type in an epitaxial layer having a first surface, and a second surface on a first surface of the semiconductor substrate, the first semiconductor region coupling the buried semiconductor region to a first node of a detection circuit via the first surface of the epitaxial layer, and a second semiconductor region of the second conductivity type in the epitaxial layer, the second semiconductor region coupling the buried semiconductor region to a second node of the detection circuit via the first surface of the epitaxial layer.

One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.

A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

A semiconductor system, a semiconductor device, a through-silicon via (TSV) test method, and a method of manufacturing a semiconductor device are provided. The semiconductor system includes a semiconductor device including a buffer die and first to L-th (where L is an integer greater than or equal to 2) stack dies stacked on the buffer die and communicating with the buffer die through N (where N is a positive integer) TSVs; and a TSV test device that measures each of voltages at one end and voltages at another end on the N TSVs according to a clock signal, compares each of the voltages at the one end and the voltages at the other end with a reference voltage, and determines whether each of the N TSVs has a plurality of TSV defect types according to comparison results.