A method includes establishing, by a diagnostic disc, a secure wireless connection with a computing system using a wireless communication circuit of the diagnostic disc before or after the diagnostic disc is placed into a processing chamber. The method further includes generating, by at least one non-contact sensor of the diagnostic disc, sensor data of a component disposed within the processing chamber. The method further includes storing the sensor data in a memory of the diagnostic disc. The method further includes wirelessly transmitting the sensor data to the computing system, using the wireless communication circuit. The method further includes terminating the secure wireless connection with the computing system and clearing the sensor data from the memory of the diagnostic disc.

Semiconductor structures and methods for manufacturing and testing semiconductor structures are provided. The semiconductor structures include an integrated circuit formed in a semiconductor substrate, a seal ring on at least a first side of the semiconductor substrate and surrounding a perimeter of the integrated circuit, an input element, an output element, and a backside metal die damage ring (BMDDR) disposed on the first side of the semiconductor substrate, extending through the semiconductor substrate, and disposed on a second side of the semiconductor substrate, the BMDDR disposed between the integrated circuit and the seal ring, the BMDDR at least partially surrounding the perimeter of the integrated circuit, the BMDDR coupled to and forming an electrical circuit between the input element and the output element.

A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a scribe line region. The scribe line region includes a test region and a dicing region adjacent to the test region. The test region includes an active element. The dicing region includes at least one layer having a plurality of patterns.

A method for fabrication of a heterogenous system on a chip (SoC) or other like integrated circuit (IC) device provides at least two dissimilar processing cores sharing a common functional profile but differentiated as to how the common functional profile is implemented. For example, the common functional profile may define the physical and logical configuration of each core, the functions and/or languages executable thereon, and any external interconnects to other devices or systems. However, each core may have a distinct implementation profile differentiated from that of the other on one or more levels of decomposition, based on differences in the underlying configuration of logical devices, the circuit components of said logical devices, and/or the physical design parameters including process geometries, fabrication standards, and/or fabrication processes via which the functional profile is physically realized in each core.

There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

A device in a chamber is provided. The device comprises at least one die. The at least one die comprise a first voltage generator, a dielectric layer and a first voltage regulator circuit. The first voltage generator is charged to have a first induced voltage by induced charges generated in response to a first voltage of a first electrode of a chuck in the chamber. The dielectric layer surrounds the first voltage generator to isolate the first voltage generator from the first electrode. The first voltage regulator circuit is coupled to the first voltage generator to receive the first induced voltage and generates a first power supply voltage according to the first induced voltage for a first circuit in the device.

Improved breakdown test structures are provided. In some embodiments, multiple test structures may be combined into a single (e.g., two-terminal) test structure for monitoring interconnect voltage breakdown (VBD) of representative interconnect structures within scribe line regions.

The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

A method of operating an electronic device for detecting a defect due to a particle in an equipment generated during a bonding process of a semiconductor chip is disclosed. For example, the method may include obtaining, by the electronic device, profile data including operation information of the equipment from the equipment during the bonding process. Additionally, the method may include calculating, by the electronic device, characteristic data of bonded chips (e.g., from the bonding process) by pre-processing the profile data. Subsequently, after the bonding process is completed, the method may include selecting, by the electronic device, a coordinate of a defective chip on a substrate as a defect coordinate by comparing result data of a reference chip and peripheral chips based on the characteristic data. In some embodiments, the result data may include respective height value information of the bonded chips.

Provided is a semiconductor package, including a first semiconductor chip, and a second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes a test pattern, and wherein a frequency based on stress being exerted on the first semiconductor chip is measured based on the test pattern.