The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

The invention provides a semiconductor structure comprising a thin film resistor layer, which comprises a metal gate, wherein the metal gate comprises a titanium nitride layer, a titanium layer and an aluminum layer stacked from bottom to top, wherein the ratio of the thickness of the aluminum layer to the thickness of the titanium layer is greater than 0.66, and a thin film resistor layer is located in a dielectric layer directly above the metal gate, wherein at least a part of the thin film resistor layer and the metal gate are overlapped from a top view. The invention has the function of reducing the probability of copper extrusion in the P-type gate structure and improving the quality of semiconductor devices.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A method of processing a substrate that includes: loading the substrate having a raised feature with at least two sidewalls exposed in a processing chamber; depositing a first layer over the substrate to cover a first portion of the two sidewalls; depositing a second layer over the first layer to cover a second portion of the two sidewalls; depositing a third layer over the second layer and the raised feature to cover a third portion of the sidewalls and a top surface of the raised feature; performing an anisotropic dry etching that removes portions of the second layer and the third layer, a remainder of the second layer forming a second sidewall spacer and a remainder of the third layer forming a third sidewall spacer; and performing an isotropic etching that selectively removes the second sidewall spacer to expose portions of the sidewalls of the raised feature.

The present invention provides a composition for treating a semiconductor device, which can preferentially form a coating film on a first surface in a case of being brought into contact with a substrate having a first surface containing a metal atom and a second surface not containing a metal atom, and can selectively form a coating film on the first surface even after storage; and a method for manufacturing a modified substrate using the composition for treating a semiconductor device. The composition for treating a semiconductor device of the present invention contains a polymer having a functional group which interacts with a surface containing a metal atom in a substrate and an ethylenically unsaturated group, a polymerization inhibitor, and a solvent.

A semiconductor device includes a semiconductor substrate including a first side, a second side, a sidewall connected to the first and second sides, and at least one protrusion protruded from the second side, devices disposed at the first side of the semiconductor substrate, and an interconnect structure disposed over the first side of the semiconductor substrate and electrically coupled to the devices. The protrusion and the semiconductor substrate are made of a same material

A method of manufacturing a three-dimensional system-on-chip, comprising providing a memory wafer structure with a first redistribution layer; disposing a first conductive structure and a core die structure and an input/output die structure with a second conductive structure on the first redistribution layer, the input/output die structure being disposed around the core die structure; forming a dielectric layer covering the core die structure, the input/output die structure, and the first conductive structure; removing a part of the dielectric layer and thinning the core die structure and a plurality of input/output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer, the third redistribution layer being electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; performing die saw. A three-dimensional system-on-chip is further provided.

The present application discloses a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a word line, a word line dielectric layer, and first and second source/drain regions. The word line is buried in the substrate. The word line dielectric layer is disposed between the substrate and the word line, and the word line dielectric layer includes: a first oxide layer and a second oxide layer. The first oxide layer is in contact with the word line and is formed by an atomic layer deposition (ALD) process. The second oxide layer is in contact with the substrate and is formed by a thermal oxidation process. The first and the second source/drain regions are disposed in the substrate and above the word line, wherein the word line is disposed laterally between the first and the second source/drain regions.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.