A semiconductor device includes a heat sink, a base material including an insulating layer and mounted on the heat sink on one side in a first direction, a first conductive layer bonded to the base material and located on a side opposite the heat sink with respect to the base material, a first semiconductor element bonded to the first conductive layer, a first power terminal electrically connected to the first conductive layer and the first semiconductor element, and a sealing resin covering the first conductive layer and the first semiconductor element. The first power terminal is exposed from the sealing resin. The first power terminal is surrounded by a peripheral edge of the sealing resin as viewed in the first direction.

An interconnect for a semiconductor device includes a first bonding pad having a first surface, a second bonding pad having a second surface bonded to the first surface of the first bonding pad, and a first guard dummy adjacent the second bonding pad and having a third surface substantially coplanar with the second surface of the second bonding pad.

A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a packaging substrate having a plurality of grooves orthogonally arranged and substantially surrounding a plurality of package sites. A plurality of semiconductor die is affixed on a first major side of the packaging substrate. Each semiconductor die of the plurality of semiconductor die is affixed at a unique package site of the plurality of package sites. An encapsulant encapsulates the first major side of the packaging substrate such that each semiconductor die of the plurality of semiconductor die is encapsulated by the encapsulant. A singulation cut is formed along each groove of the plurality of grooves of the packaging substrate to form individual semiconductor device units.

An electronic package and a manufacturing method thereof are provided, including a first electronic component disposed on a first side of a first substrate disposed on a first surface of a circuit board, a plurality of bonding wires formed on the first side of the first substrate for electrically connecting the first substrate to the circuit board. A second electronic component is disposed on the first surface of the circuit board for the first electronic component to be electrically connected to the second electronic component via the first substrate, the plurality of bonding wires and the circuit board in sequence. A first encapsulant is formed on the first surface of the circuit board to cover the first substrate, the first electronic component and the plurality of bonding wires. Thereby, the present disclosure can effectively reduce the size of the first substrate and the electronic package.

A semiconductor package includes: a first redistribution structure; a first chip disposed on the first redistribution structure; a molding member at least partially surrounding the first chip and disposed on the first redistribution structure; a plurality of conductive pillars penetrating the molding member in a vertical direction; a support structure disposed between adjacent conductive pillars of the plurality of conductive pillars and disposed on the first redistribution structure; a second redistribution structure disposed on the molding member, the plurality of conductive pillars, and the support structure; a second chip disposed on the second redistribution structure and overlapping the plurality of conductive pillars; and a heat dissipation chip overlapping the first chip in the vertical direction.

A semiconductor package assembly, comprising: a semiconductor package comprising: a semiconductor die mounted on a substrate; a pair of interconnection blocks mounted at opposite sides of the semiconductor die; and an encapsulant layer, wherein the pair of interconnection blocks have respective top surfaces exposed and a top surface of the semiconductor die is exposed; and an inductor block mounted on the semiconductor package, comprising: an inductor extending through the insulation body in a horizontal direction, and having a pair of inductor contact pads exposed at a bottom surface of the insulation body, wherein the pair of inductor contact pads are aligned to and electrically coupled to the pair of interconnection blocks; and a thermally conductive coating formed at an outer surface of the insulation body and extending in a vertical direction of the insulation body from the bottom surface to a top surface of the insulation body.

A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.

Disclosed are an intelligent power module and a manufacturing method thereof, which relate to the technical field of electronic devices. The intelligent power module includes a substrate, wherein a chip and a plurality of conductive pins are arranged on the substrate, one end of each of the conductive pins is connected to the chip, and a solder pin is formed at an end portion of the other end of the conductive pin; and an external pin frame, including a plurality of leads, and a connection structure is formed at an end portion of one end of each of the lead; and the connection structure includes a connection portion, and support portions, wherein an arrangement direction of the support portions is the same as that of the solder pins, an accommodation space is formed between the two support portions, and the solder pin is located between the two support portions.