An electronic device includes a substrate, an outer layer, a conductive line layer, and a switchable circuit chip. The substrate has a plurality of having a plurality of first vias. The outer layer is disposed on a side of the substrate and has a plurality of second vias. The first vias have a larger distribution density or quantity than the second vias, so that a part of the first vias are electrically connected to the second vias, and another part of the first vias are electrically floating. The conductive line layer is disposed on the outer layer and has a plurality of conductive traces. The conductive traces are electrically connected to the second vias. The switchable circuit chip is electrically connected to the first vias. The conductive traces are electrically connected to the switchable circuit chip. The switchable circuit chip is configured for controlling an electrical connecting relationship between the conductive traces and the first vias and an electrical connecting relationship among the conductive traces.

An electronic package structure and manufacturing method thereof. The electronic package structure includes a circuit board, an interposer, a chip, a circuit structure, and a coaxial conductive element. The interposer is disposed on the circuit board. The interposer has a through groove. The chip is disposed in the through groove and located on the circuit board to electrically connect with the circuit board. The circuit structure is disposed on the interposer. The coaxial conductive element penetrates the interposer to electrically connect the circuit structure and the circuit board. The coaxial conductive element includes a first conductive structure, a second conductive structure, and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure.

A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

A method of forming a semiconductor structure includes forming a photoresist over a first conductive pattern. The method further includes patterning the photoresist to define a plurality of first openings. The method further includes depositing a conductive material in each of the plurality of first openings. The method further includes disposing a molding material over the first conductive pattern, wherein the molding material surrounds a die. The method further includes removing a portion of the molding material to form a second opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a redistribution structure over the molding material and the dielectric member, wherein the redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.

A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Molded device packages which allow electrical contacts to coupled to a first surface of a circuit substrate such as a printed circuit board while allowing the opposite surface to remain exposed for other purposes such as bonding thermal structures such as heatsinks include electrically-conductive pillars which are bonded to the first surface of the substrate and encapsulated in molding material. The molding material can one or more cavities over disposed over the first surface of the substrate which can be evacuated or gas-filled. The electrically-conductive pillars protrude from connected manifold and are joined to each other by a frame portion of the manifold. The manifold is patterned with a masking material that protects the pillars from being etched during a selective etching process which removes the frame portion of the manifold to separate the electrically-conductive pillars from each other.

In one example, an electronic device includes a substrate having an upper side, a lower side opposite to the upper side, a lateral side connecting the upper side to the lower side, and a conductive structure. An electronic component is coupled to the conductive structure at the upper side of the substrate. An encapsulant covers a lateral side of the electronic component and the upper side of the substrate and having an encapsulant top side and an encapsulant lateral side. The electronic device includes first metallic coating having a first metallic coating top side, a first metallic coating sidewall; and a first metallic coating thickness. The electronic device includes a second metallic coating having a second metallic coating thickness that is greater than the first metallic coating thickness. In the present example, the first metallic coating top side is over the encapsulant top side, the first metallic coating sidewall is over the encapsulant lateral side, and the second metallic coating is over the encapsulant top side. Other examples and related methods are also disclosed herein.

A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

A method of manufacturing a three-dimensional system-on-chip, comprising providing a memory wafer structure with a first redistribution layer; disposing a first conductive structure and a core die structure and an input/output die structure with a second conductive structure on the first redistribution layer, the input/output die structure being disposed around the core die structure; forming a dielectric layer covering the core die structure, the input/output die structure, and the first conductive structure; removing a part of the dielectric layer and thinning the core die structure and a plurality of input/output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer, the third redistribution layer being electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; performing die saw. A three-dimensional system-on-chip is further provided.