H10P14/3416

Deposition of boron nitride films using hydrazido-based precursors

A method of forming high quality a-BN layers. The method includes use of a precursor chemistry that is particularly suited for use in a cyclical deposition process such as in chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In brief, new methods are described of forming boron nitride (BN) layers from precursors capable of growing amorphous BN (a-BN) films by CVD, ALD, or the like. In some cases, the precursor is or includes a borane adduct of hydrazine or a hydrazine derivative.

Group III element nitride substrate and production method for group III element nitride substrate

A Group-III element nitride substrate includes a first main surface and a second main surface facing each other, wherein, in the first main surface, crystallinity of a first part positioned on a central portion thereof is higher than crystallinity of a second part positioned outside the first part.

Semiconductor device

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a third nitride region. The first nitride region includes Al.sub.x1Ga.sub.1-x1N (0x1<1). The first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second nitride region includes Al.sub.x2Ga.sub.1-x2N (x1<x21) or In.sub.yAl.sub.zGa.sub.(1-y-z)N (0<y1, 0z<1, y+z1). The second nitride region includes a sixth partial region. The third nitride region includes Al.sub.x3Ga.sub.1-x3N (x1<x3<x2). The third nitride region includes a seventh partial region.

Method to improve performances of tunnel junctions grown by metal organic chemical vapor deposition

A device including an activated p-type layer comprising a III-Nitride based Mg-doped layer grown by vapor phase deposition or a growth method different from MBE. The p-type layer is activated through a sidewall of the p-type layer after the removal of defects from the sidewall thereby increasing a hole concentration in the p-type layer. In one or more examples, the device includes an active region between a first n-type layer and the p-type layer; a second n-type layer on the p-type layer; and a tunnel junction between the second n-type layer and the p-type layer, and the activated p-type layer has a hole concentration characterized by a current density of at least 100 Amps per centimeter square flowing between the first n-type layer and the second n-type layer in response to a voltage of 4 volts or less applied across the first n-type layer and the second n-type layer.

VARIABLE COMPOSITION TERNARY COMPOUND SEMICONDUCTOR ALLOYS, STRUCTURES, AND DEVICES
20260040742 · 2026-02-05 ·

In.sub.xAl.sub.yGa.sub.1-x-yN semiconductor structures having optoelectronic elements characterized by epitaxial layers having different in-plane a-lattice parameters and different InN mole fractions are disclosed. The active regions are configured to emit radiation in different wavelength ranges and are characterized by strain states within about 1% to 2% of compressive strain. The epitaxial layers are grown on patterned In.sub.xAl.sub.yGa.sub.1-x-yN seed regions on a single substrate, where the relaxed InGaN growth layers provide (0001) In.sub.xAl.sub.yGa.sub.1-x-yN growth surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions. In.sub.xAl.sub.yGa.sub.1-x-yN semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and in display applications.

Growth-anneal cycling of a semiconductor layer

A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

Relaxed Wurtzite Ingan layers

Bulk relaxed Wurtzite In-containing III-nitride layers having a smooth and substantially pit-free surface morphology and an interface region having a substantially relaxed in-plane a-lattice parameter and characterized by a single-phase gallium-polar (0001) orientation are disclosed. Methods of making the bulk relaxed Wurtzite In-containing III-nitride layers using MOCVD growth conditions are also disclosed. Semiconductor structures include epitaxial layers grown on a bulk relaxed Wurtzite In-containing III-nitride layer. The semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and display applications.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a gallium nitride-based semiconductor device. The semiconductor device includes: a substrate; an epitaxial layer on the substrate; a first aluminum-containing layer on the epitaxial layer; a source terminal, a drain terminal, and a gate terminal on the first aluminum-containing layer, wherein the gate terminal is between the source terminal and the drain terminal; a second aluminum-containing layer over the first aluminum-containing layer and between the gate terminal and the drain terminal; and a third aluminum-containing layer over the second aluminum-containing layer. The first aluminum-containing layer has a first concentration of aluminum, the second aluminum-containing layer has a second concentration of aluminum, and the third aluminum-containing layer has a third concentration of aluminum. The second concentration is substantially greater than the first concentration, and the second concentration is substantially greater than the third concentration.

CUBIC GAN SEMICONDUCTOR DEVICE MANUFACTURING METHODS
20260068552 · 2026-03-05 · ·

A method for fabricating a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a groove exposing different crystal facing a planar surface; depositing a buffer layer over the substrate; epitaxially growing a semiconductor layer over the buffer layer, whereby least a portion of the buffer layer exhibits a cubic crystalline phase structure.

VERTICAL GALLIUM NITRIDE CONTAINING FIELD EFFECT TRANSISTOR WITH SILICON NITRIDE PASSIVATION AND GATE DIELECTRIC REGIONS

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.