In a first step S101, a first region in which a polarity inversion layer is formed, and a second region in which the polarity inversion layer is not formed are provided on a substrate. Next, in a second step S102, a first nitride semiconductor is epitaxially grown on the substrate having the first region and the second region along the c-axis direction such that a first semiconductor layer is formed. Next, in a third step S103, a second nitride semiconductor is epitaxially grown on the first semiconductor layer along the c-axis direction such that a second semiconductor layer is formed on the first semiconductor layer. The second nitride semiconductor has different polarization, electron affinity, and band-gap energy from the first nitride semiconductor. The second semiconductor layer forms a heterojunction with the first semiconductor layer. The interface therebetween has a polarization charge, which is positive or negative depending on polarity.

A nitride semiconductor and method of making the same are provided. In embodiments, a method for manufacturing a nitride semiconductor includes: providing a nitride semiconductor material including at least one main dopant defining a p-type portion; doping the nitride semiconductor material with at least one co-dopant co-located with the main dopant, wherein the co-dopant reduces gas-enhanced diffusion of the main dopant by a component in an ambient gas during annealing; and annealing the nitride semiconductor material under pressure, thereby producing an annealed nitride semiconductor material with an activated main dopant. In implementations, a nitride semiconductor is produced including an annealed nitride semiconductor material doped with magnesium (Mg) and oxygen (O) in an activated p-type portion, wherein the Mg and O are present at a ratio of 2:1.

The present application provides a substrate and a manufacturing method therefor. The substrate includes a silicon substrate and a protective layer, the silicon substrate includes a middle part and an edge part, and a thickness of the middle part is greater than a thickness of the edge part. The middle part has a to-be-grown surface, and a crystal orientation of the to-be-grown surface is different from a crystal orientation of surface of the edge part. The protective layer covers the edge part and is configured to prevent defects in the edge part from extending to the middle part during high-temperature processing.

A single crystal silicon substrate with a nitride semiconductor layer, including: a single crystal silicon substrate; a 3C-SiC single crystal film epitaxially grown on the single crystal silicon substrate; and a nitride semiconductor layer epitaxially grown on the 3C-SiC single crystal film. Dislocations are formed throughout the single crystal silicon substrate, a length (dislocation length) of each of the dislocations when seen in a planar projection onto the single crystal silicon substrate is greater than or equal to 1 mm, and a density of the dislocations is greater than or equal to 10/cm.sup.2. This provides a single crystal silicon substrate with a nitride semiconductor layer having a large diameter such as 200 mm or 300 mm that is made using a regular thickness Si substrate and has less warpage and especially no cracks, and a method for producing such a single crystal silicon substrate with a nitride semiconductor layer.

A method for forming a III-nitride semiconductor device involves determining work functions of a first III-nitride contact layer and a first metal contact. The determined work function of the first III-nitride contact layer is based on a group III element of the first III-nitride contact layer. Based on the determined work functions of the first III-nitride contact layer and of the first metal contact, it is determined that the work function of the first III-nitride contact layer should be adjusted. The III-nitride semiconductor device is formed including the first III-nitride contact layer adjacent to a second III-nitride contact layer, the first metal contact arranged on the first III-nitride contact layer, and a second metal contact arranged on the second III-nitride contact layer. The first III-nitride contact layer of the formed III-nitride semiconductor device is a boron nitride alloy having an amount of boron that adjusts the work function of the first III-nitride contact layer relative to the determined work function of the first metal layer based on the group III element of the first III-nitride contact layer.

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

A semiconductor structure and the manufacturing method thereof are provided. The semiconductor structure comprises a silicon substrate, a nitride buffer composite layer, an active layer and a silicon barrier composite layer. The nitride buffer composite layer is disposed above the silicon substrate, the active layer is disposed above the nitride buffer composite layer, and the silicon barrier composite layer is interposed within the nitride buffer composite layer to substantially block the diffusion of silicon impurities from the silicon substrate to reduce leakage current.

Provided are a substrate processing method and a substrate processing apparatus for forming a thin boron nitride film on a substrate. A substrate processing method includes: preparing a substrate including a foundation layer; forming a boron-containing material layer on the substrate by exposing the substrate to a first boron-containing gas; forming a nucleus of a boron nitride-containing material by exposing the substrate on which the boron-containing material layer is formed to a plasma of a first processing gas containing a first nitrogen-containing gas and nitriding the boron-containing material layer; and forming a boron nitride film on the substrate by exposing the substrate on which the nucleus of the boron nitride-containing material is formed to a plasma of a second processing gas containing a second boron-containing gas and a second nitrogen-containing gas different from the first nitrogen-containing gas.

The invention relates to a method for obtaining a layer at least partially made of a nitride (N), first comprising the provision of a stack comprising at least one assembly of pads (1000A1-1000B4) extending from a substrate (100). Each pad comprises at least one creep section (220A1-220A5) and one crystalline section (300A1,300A5) surmounting the creep section (200A1-200A5). Then, a crystallite (510A1-510A5) is epitaxially grown on at least some of said pads until coalescence of the crystallites, so as to form a nitride layer (550A). The pads of the assembly are distributed over the substrate, such that the relative arrangement of the pads of the assembly is such that during the epitaxy of the crystallites, the progressive coalescence of the crystallites is always done between, on the one hand, a crystallite or a plurality of coalesced crystallites and, on the other hand, an isolated crystallite.

There is a method for making a substrate by providing a Si top surface in a plane, and providing a GaN top surface in the plane adjacent the Si top surface, wherein a substrate is formed having a top surface comprising the Si top surface and the GaN top surface. There is a substrate having a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface. There is a package having a substrate with a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface, a CMOS chip attached to the Si top surface, a GaN transistor attached to the GaN top surface, and a metal layer connecting the CMOS chip and the GaN transistor.