A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

The present invention is a group-III nitride semiconductor wafer including a group-III nitride semiconductor film on a substrate for film formation, in which in a cross-sectional shape of a surface of the substrate for film formation of a chamfered portion of the substrate in a diameter direction, a chamfering angle (.sub.1) relative to the surface of the substrate is 21 or more and 23 or less, and on the surface of the substrate in a diameter direction, a chamfering width (X.sub.1) is 500 m or more and 1000 m or less, which is a distance between an outer peripheral end portion of the substrate for film formation and an inner peripheral end portion of the chamfered portion. Thereby, the group-III nitride semiconductor wafer, in which the group-III nitride semiconductor film is provided on the substrate for film formation, and the method for producing the same are provided.

A method of processing a silicon surface includes using a first radical species to remove contamination from the surface and to roughen the surface; and using a second radical species to smooth the roughened surface. Reaction systems for performing such a method, and silicon surfaces prepared using such a method, also are provided.

A silicon wafer is provided in which a dopant is phosphorus, resistivity is from 0.5 m.Math.cm to 1.2 m.Math.cm, and carbon concentration is 3.010.sup.16 atoms/cm.sup.3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

The present invention relates to a layer formation method and, more specifically, to a semiconductor device manufacturing method for forming a semiconductor device through a low-temperature process. The layer formation method according to an embodiment of the present invention is a method for manufacturing a semiconductor device which comprises a silicon substrate containing germanium (Ge) or a substrate on which a silicon layer containing germanium (Ge) is formed, and which comprises an undoped gallium nitride (GaN) layer, an N-type gallium nitride (GaN) layer, an active layer and a P-type gallium nitride (GaN) layer, wherein a step of forming at least one gallium nitride layer from among the undoped gallium nitride (GaN) layer, the N-type gallium nitride (GaN) layer, the active layer and the P-type gallium nitride (GaN) layer comprises the steps of: a) sequentially supplying a gallium (Ga) precursor and a nitrogen (N2) precursor at 500 C. or lower, thereby forming a gallium nitride (GaN) layer on the substrate; and b) exposing the gallium nitride (GaN) layer to a hydrogen-containing plasma, and steps a) and b) are repeated multiple times.

There are provided (a) heat-treating a substrate including a film containing a group 14 element at a first temperature; (b) heat-treating the substrate at a second temperature higher than the first temperature; and (c) exposing the substrate to a treatment agent containing at least one of O and H after performing (a) and before performing (b).

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

Disclosed are methods of forming PN junction structures, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated by the same. The method of forming a PN junction structure includes: forming on a substrate a first material layer that includes first transition metal atoms and first chalcogen atoms, loading the first material layer into a process chamber and supplying a gas of second chalcogen atoms, and forming a second material layer by substituting the second chalcogen atoms for the first chalcogen atoms on a selected portion of the first material layer. The first material layer has one of n-type conductivity and p-type conductivity. The second material layer has the other of the n-type conductivity and the p-type conductivity.

A method of forming a support substrate having a charge-trapping layer involves introducing a single-crystal silicon base substrate into a deposition chamber and, without removing the base substrate from the chamber and while flushing the chamber with a precursor gas, forming an intrinsic silicon epitaxial layer on the base substrate, then forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period, and then forming a polycrystalline silicon charge-trapping layer on the dielectric layer by introducing a precursor gas into the chamber over a second time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature of between 1010 C. and 1200 C.

A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.