A support substrate for a radiofrequency application comprises: a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm.Math.cm and strictly less than 500 ohm.Math.cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm.Math.cm, a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm.Math.cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.

Disclosed are a semiconductor comprising amorphous tellurium oxide, thin film transistor and method of fabricating same. In detail, a semiconductor comprising a chalcogen atom comprising at least one selected from the group consisting of a sulfur atom (S) and a selenium atom (Se); and tellurium composite comprising a tellurium (Te) atom and tellurium oxide. A thin film transistor (TFT) fabricated based on the TeO.sub.x channel layer according to the present disclosure exhibits excellent output/transfer characteristics and superior electrical performance with high hole field-effect mobility and a high on/off current ratio of 10.sup.7.

A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

Methods for forming structures that include forming a heteroepitaxial layer on a substrate are disclosed. The presently disclosed methods comprise epitaxially forming a buffer layer on the substrate. The substrate has a substrate composition. The buffer layer has a buffer layer composition. The buffer layer composition is substantially identical to the substrate composition. The presently disclosed methods further comprise epitaxially forming a heteroepitaxial layer on the buffer layer. The heteroepitaxial layer has a heteroepitaxial layer composition which is different from the substrate composition.

Bulk relaxed Wurtzite In-containing III-nitride layers having a smooth and substantially pit-free surface morphology and an interface region having a substantially relaxed in-plane a-lattice parameter and characterized by a single-phase gallium-polar (0001) orientation are disclosed. Methods of making the bulk relaxed Wurtzite In-containing III-nitride layers using MOCVD growth conditions are also disclosed. Semiconductor structures include epitaxial layers grown on a bulk relaxed Wurtzite In-containing III-nitride layer. The semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and display applications.

A method for fabricating a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a groove exposing different crystal facing a planar surface; depositing a buffer layer over the substrate; epitaxially growing a semiconductor layer over the buffer layer, whereby least a portion of the buffer layer exhibits a cubic crystalline phase structure.

The method provides for the growth of an epitaxial layer (200) made of a first semiconductor material on a substrate (100) made of a second semiconductor material; the materials are different and have different CTEs; the method comprises the steps of: A) patterning the substrate (100) by an etching process so to form an array of pillars (110), the pillars (110) being laterally spaced from each other and having a top section (112) larger than a bottom section (114) and/or intermediate sections (116), B) depositing the second semiconductor material on top of the pillars (110) at a growth temperature so to form an epitaxial layer (200) generated by vertical and lateral growth, and C) inducing breaking of the pillars (110) by cooling the substrate (100) and the epitaxial layer (200) below the growth temperature.

The present application provides a substrate and a manufacturing method therefor. The substrate includes a silicon substrate and a protective layer, the silicon substrate includes a middle part and an edge part, and a thickness of the middle part is greater than a thickness of the edge part. The middle part has a to-be-grown surface, and a crystal orientation of the to-be-grown surface is different from a crystal orientation of surface of the edge part. The protective layer covers the edge part and is configured to prevent defects in the edge part from extending to the middle part during high-temperature processing.

A single crystal silicon substrate with a nitride semiconductor layer, including: a single crystal silicon substrate; a 3C-SiC single crystal film epitaxially grown on the single crystal silicon substrate; and a nitride semiconductor layer epitaxially grown on the 3C-SiC single crystal film. Dislocations are formed throughout the single crystal silicon substrate, a length (dislocation length) of each of the dislocations when seen in a planar projection onto the single crystal silicon substrate is greater than or equal to 1 mm, and a density of the dislocations is greater than or equal to 10/cm.sup.2. This provides a single crystal silicon substrate with a nitride semiconductor layer having a large diameter such as 200 mm or 300 mm that is made using a regular thickness Si substrate and has less warpage and especially no cracks, and a method for producing such a single crystal silicon substrate with a nitride semiconductor layer.

Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.