A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 , respectively, so as to realize the flatness of the silicon-on-insulator film.

The invention relates to a method for obtaining a layer at least partially made of a nitride (N), first comprising the provision of a stack comprising at least one assembly of pads (1000A1-1000B4) extending from a substrate (100). Each pad comprises at least one creep section (220A1-220A5) and one crystalline section (300A1,300A5) surmounting the creep section (200A1-200A5). Then, a crystallite (510A1-510A5) is epitaxially grown on at least some of said pads until coalescence of the crystallites, so as to form a nitride layer (550A). The pads of the assembly are distributed over the substrate, such that the relative arrangement of the pads of the assembly is such that during the epitaxy of the crystallites, the progressive coalescence of the crystallites is always done between, on the one hand, a crystallite or a plurality of coalesced crystallites and, on the other hand, an isolated crystallite.

A method for forming an epitaxial stack on a plurality of substrates comprises providing a plurality of substrates to a process chamber and executing deposition cycles, wherein each deposition cycle comprises a first deposition pulse and a second deposition pulse. The epitaxial stack comprises a first epitaxial layer stacked alternatingly and repeatedly with a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer having a first native lattice parameter. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer having a second native lattice parameter, wherein the first native lattice parameter lies in a range within 1.5% larger than and 0.9% smaller than the second native lattice parameter.

A semiconductor chip includes a semiconductor substrate, a semiconductor device layer, and an insulation layer. The semiconductor substrate extends from first and second surfaces that are spaced apart and includes first and second regions with distinct single crystal structures. The semiconductor device layer is positioned on one surface of the semiconductor substrate, and the insulation layer envelops at least the upper and side surfaces of the semiconductor device layer. A plurality of penetration holes may be formed in the insulation layer. A laser may irradiate the semiconductor substrate to form the crystal structures. The laser may irradiate through the plurality of penetration holes.

A method of processing a silicon surface includes using a first radical species to remove contamination from the surface and to roughen the surface; and using a second radical species to smooth the roughened surface. Reaction systems for performing such a method, and silicon surfaces prepared using such a method, also are provided.

A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.

A method for manufacturing a group III nitride semiconductor substrate, that includes: growing a first AlN buffer layer on an Si substrate at a first growth temperature; growing a second AlN buffer layer on the first AlN buffer layer at a second growth temperature higher than the first growth temperature; and growing a group III nitride semiconductor layer on the second AlN buffer layer, wherein an Al raw material and an N raw material are alternately repeatedly fed in the growing the first AlN buffer layer.

A wafer includes a buried substrate; a layer of silicon (100) disposed on the buried substrate and forming multiple U-shaped grooves, wherein each U-shaped groove comprises a bottom portion and silicon sidewalls (111) at an angle to the buried substrate; a buffer layer disposed within the multiple U-shaped grooves; and multiple gallium nitride (GaN)-based structures having vertical sidewalls disposed within and protruding above the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).

The present invention is a nitride semiconductor wafer, including: a silicon single-crystal substrate; and a device layer composed of a nitride semiconductor above the silicon single-crystal substrate, wherein the silicon single-crystal substrate is a CZ silicon single-crystal substrate, and has a resistivity of 1000 .Math.cm or more, an oxygen concentration of 5.010.sup.16 atoms/cm.sup.3 (JEIDA) or more and 2.01.0.sup.17 atoms/cm.sup.3 (JEIDA) or less, and a nitrogen concentration of 5.010.sup.14 atoms/cm.sup.3 or more. This provides a nitride semiconductor wafer that hardly causes plastic deformation even using a high-resistant low-oxygen silicon single-crystal substrate produced by the CZ method, which is suitably used for a high-frequency device, and that can reduce warpage of the substrate.