An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a multi-layer patterned absorber layer on the reflective multilayer stack is provided. Disclosed embodiments include an absorber layer that includes an alloy comprising ruthenium (Ru), chromium (Cr), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), tungsten (W) or palladium (Pd), and at least one alloying element. The at least one alloying element includes ruthenium (Ru), chromium (Cr), tantalum (Ta), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), hafnium (Hf), boron (B), nitrogen (N), silicon (Si), zirconium (Zr) or vanadium (V). Other embodiments include a multi-layer patterned absorber structure with layers that include an alloy and an alloying element, where at least two of the layers of the multi-layer structure have different compositions.

A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

A method for processing a substrate includes receiving the substrate on a substrate holder disposed in a processing chamber, the substrate including a layer to be processed and a patterned mask disposed over the layer to be processed. The method further includes flowing a processing gas into the processing chamber, and replacing a material of the patterned mask with a metal of the processing gas to form a metal patterned mask occupying a same location as the patterned mask. And the method further includes etching, using the metal patterned mask as an etch mask, the layer to be processed to form a patterned layer, the patterned layer including feature openings.

A method is disclosed for producing an array of parallel conductive lines in a first level of a multilevel interconnect structure of a semiconductor component. The lines are produced by direct etching (a conductive layer is produced), a hardmask line pattern is formed on the conductive layer and the line pattern is transferred to the conductive layer by etching the conductive layer relative to the hardmask lines. The hardmask lines are reduced in width prior to the pattern transfer. The width reduction is done at intended via locations. Local hardmask pillars are produced on the hardmask lines prior to the width reduction step, so that the original line width is maintained at the intended via locations. As a result, the width of the conductive lines obtained after the pattern transfer is smaller compared to conventional configurations, except in local areas corresponding to the locations of interconnect vias.

A plasma processing method includes: (a) providing a substrate to a substrate support; and (b) forming a deposited film on a surface of the substrate before etching an etching target film, and removing a part of the deposited film. (b) repeats a cycle including a first period in which a source RF signal is supplied to a chamber and a bias signal is supplied to the substrate support, a second period in which the source RF signal with a lower power level is supplied to the chamber and the bias signal with a higher power level is supplied to the substrate support, as compared to the first period, and a third period in which the source RF signal with a lower power level is supplied to the chamber and the bias signal with a higher power level is supplied to the substrate support, as compared to the second period.

A substrate, a first layer disposed on the substrate, and a second layer disposed on the first layer are provided. An opening is etched through the second layer to the first layer. A first portion of the first layer is etched through the opening using a first etchant, to expose a surface of the substrate through the opening. A feature is deposited on the surface of the substrate through the opening. A second portion of the first layer is etched using a gaseous etchant, to release the substrate from the second layer.

A method for forming ultraviolet (UV) radiation responsive metal-oxide containing film is disclosed. The method may include, depositing an UV radiation responsive metal oxide-containing film over a substrate by, heating the substrate to a deposition temperature of less than 400 C., contacting the substrate with a first vapor phase reactant comprising a metal component, a hydrogen component, and a carbon component, and contacting the substrate with a second vapor phase reactant comprising an oxygen containing precursor, wherein regions of the UV radiation responsive metal oxide-containing film have a first etch rate after UV irradiation and regions of the UV radiation responsive metal oxide-containing film not irradiated with UV radiation have a second etch rate, wherein the second etch rate is different from the first etch rate.

A substrate processing method according to the present invention incudes: a preparation step of preparing a substrate in which at least a first surface containing silicon oxide and a second surface containing silicon or a silicon compound other than silicon oxide are exposed; a surface modification step of forming an etching selectivity imparting film on at least a part of the first surface and at least a part of the second surface by a silylation treatment of bringing a silylating agent into contact with the first surface and the second surface; and an etching step of selectively carrying out an etching treatment on the second surface with respect to the first surface using an etching agent after the surface modification step.

A method of forming a semiconductor device includes forming a row of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells arranged alternatingly with the n-type wells, forming trigger regions in between the n-type wells and the p-type wells, the trigger regions including a low-doped section of the semiconductor body that is configured to induce current flow between the p-type wells and the n-type wells via avalanche breakdown, wherein the p-type wells and the n-type wells are formed by implanting dopant atoms into the upper surface of the semiconductor body, and wherein the low-doped section of the semiconductor body is formed by a hardmask that prevents the dopant atoms from penetrating the upper surface of the semiconductor body during the implanting of the dopant atoms.

A mask apparatus for x-ray lithography and metrology where the x-ray absorber material is embedded in diamond and then covered with a thermally conductive material to provide requisite thermal conductivity when irradiated with x-rays. The apparatus then includes a hollow holder that is thermally interfaced with the mask and may also include means for external thermal control. The mask apparatus allows for transmission of x-rays from a lithography beam as well as metrology beams of other wavelengths including UV, IR, visible, and others.