A semiconductor device is disclosed herein. The semiconductor device includes a first conductive feature disposed over a substrate and a silicon carbon nitride (SiCN) layer disposed over the first conductive feature, wherein the SiCN layer has a nitrogen concentration of greater than about 30% and a carbon concentration of less than about 10%.

A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a subtractively formed via located on top of a lower level metal line. The subtractively formed via has a bottom portion and a top portion. The semiconductor interconnect structure further includes a selectively grown region formed onto the top portion of the subtractively formed via. A portion of the selectively grown region overhangs the bottom portion of the subtractively formed via in one or more directions.

A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.

A semiconductor structure includes a substrate; a top metal layer disposed in a top inter-metal dielectric (IMD) layer on the substrate; a first passivation layer covering the top metal layer and the top IMD layer; a pad layer disposed on the first passivation layer and electrically connected to the top metal layer; a spin-on glass (SOG) layer covering the pad layer and the first passivation layer; and a second passivation layer disposed on the SOG layer.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

A semiconductor device includes a substrate having an active region; a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; a via contact disposed in the first insulating layer and electrically connected to the active region; an interconnection structure disposed in the second insulating layer and electrically connected to the via contact; and an etch stop layer disposed between the first insulating layer and the second insulating layer. The etch stop layer includes an upper layer region, a lower layer region and an intermediate film between the upper layer region and the lower layer region. Each of the upper layer region and the lower layer region includes a compound that includes a first element, and an intermediate film includes a second element intermixed with the first element.

A semiconductor structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first via structure in a first dielectric layer, the first via structure including a first contact via surface. At least a portion of the first via structure is in direct contact with the first dielectric layer. The second semiconductor structure includes a second via structure in a second dielectric layer, the second via structure including a second contact via surface. At least a portion of the second via structure is in direct contact with the second dielectric layer. The first contact via surface is bonded with the second contact via surface. The second contact via surface and the first contact via surface have an overlapping interface in the vertical direction. A first barrier layer is formed at a non-overlapping interface in the first contact via surface and the second contact via surface. The first barrier layer contains a multi-component oxide.

A method for forming a semiconductor structure includes forming a conductive structure in a first dielectric layer, the conductive structure including an terminal portion and an extending portion, forming a second dielectric layer on the first dielectric layer, forming a first opening through the second dielectric layer directly above the extending portion and a second opening through the second dielectric layer directly above the terminal portion, a width of the second opening being smaller than 50% of a width of the first opening, forming a conductive material layer on the second dielectric layer and filling the first opening and the second opening, and performing a chemical mechanical polishing process to remove the conductive material layer outside the first opening and the second opening to obtain a conductive via in the first opening and a dummy via in the second opening.

A conformal nitride-rich carbide layer located on a dielectric-on-dielectric layer (a dielectric layer located on an interlayer dielectric) and metal line cap layers in an interconnect stack of an integrated circuit structure provides for improved electromigration. The carbide layer can enable integrated circuit structures to have a reduced topography prior to etch stop stack formation. In addition to enabling improved electromigration of the metal lines the carbide layers can reduce the current leakage between metal lines and nearby vias.

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion directly and physically connected to the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, a dummy via through the second dielectric layer and directly contacting the terminal portion, wherein the dummy via comprises a lower portion consisting of a first filling layer and an upper portion consisting of a second filling layer, wherein the first filling layer and the second filling layer comprise different materials.