Semiconductor structure and fabrication method thereof

Abstract

A semiconductor structure includes a substrate; a top metal layer disposed in a top inter-metal dielectric (IMD) layer on the substrate; a first passivation layer covering the top metal layer and the top IMD layer; a pad layer disposed on the first passivation layer and electrically connected to the top metal layer; a spin-on glass (SOG) layer covering the pad layer and the first passivation layer; and a second passivation layer disposed on the SOG layer.

Claims

1. A semiconductor structure, comprising: a substrate; at least two top metal layers disposed in a top inter-metal dielectric (IMD) layer on the substrate; a first passivation layer covering the at least two top metal layers and the top IMD layer; at least two pad layers disposed on the first passivation layer and electrically connected to the at least two top metal layers, respectively; a recessed region disposed between the at least two pad layers and extended into the first passivation layer; a spin-on glass (SOG) layer covering the pad layer and the first passivation layer and filled into the recessed region; and a second passivation layer disposed on the SOG layer, wherein the SOG layer is in direct contact with the at least two pad layers.

2. The semiconductor structure according to claim 1, wherein the at least two pad layers are aluminum pad layers.

3. The semiconductor structure according to claim 1, wherein the at least two top metal layers are copper layers.

4. The semiconductor structure according to claim 1, wherein the SOG layer has a flat top surface.

5. The semiconductor structure according to claim 1, wherein a partial top surface of the SOG layer is higher than a top surface of the at least two pad layers.

6. The semiconductor structure according to claim 5, wherein the SOG layer is in direct contact with sidewalls and the top surface of the at least two pad layers.

7. The semiconductor structure according to claim 1, wherein the first passivation layer is a silicon oxide layer.

8. The semiconductor structure according to claim 1, wherein the second passivation layer is a silicon nitride layer.

9. The semiconductor structure according to claim 1, wherein the second passivation layer is in direct contact with the SOG layer.

10. The semiconductor structure according to claim 1 further comprising: via plugs in the first passivation layer to electrically connect the at least two pad layers with the at least two top metal layers, respectively; and a liner layer between the via plugs and the first passivation layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 to FIG. 3 are schematic diagrams illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.

DETAILED DESCRIPTION

(2) In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

(3) Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

(4) Please refer to FIG. 1 to FIG. 3, which are schematic diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present invention. As shown in FIG. 1, first, a substrate 100, for example, a semiconductor substrate is provided. A top metal layer 112 is formed in a top inter-metal dielectric (IMD) layer 110 on the substrate 100. According to an embodiment of the present invention, the top IMD layer 110 may include an ultra-low dielectric constant (ULK) material layer. According to an embodiment of the present invention, the top metal layer 112 may be a copper layer, for example, a damascene copper layer formed by using a copper damascene process.

(5) Subsequently, a first passivation layer 120 is formed to cover the top metal layer 112 and the top IMD layer 110. According to an embodiment of the present invention, the first passivation layer 120 may be a silicon oxide layer. Next, a pad layer 130 is formed on the first passivation layer 120. According to an embodiment of the present invention, the pad layer 130 may be an aluminum pad layer. According to an embodiment of the present invention, the pad layer 130 is electrically connected to the top metal layer 112 through a via plug 124 formed in the first passivation layer 120.

(6) According to an embodiment of the present invention, the via plug 124 may be an aluminum via plug. According to an embodiment of the present invention, a liner layer 126 may be further formed between the via plug 124 and the first passivation layer 120. According to embodiments of the present invention, the liner layer 126 may comprise tantalum or tantalum nitride, for example. According to the embodiment of the present invention, at this point, a recessed region S is formed between the pad layers 130.

(7) According to an embodiment of the present invention, next, as shown in FIG. 2, a spin-on glass (SOG) layer 140 covering the pad layer 130 and the first passivation layer 120 is formed. For example, a spin coating solution composed of silicon and oxy-organic compound (Si.sub.xO.sub.yC.sub.zH.sub.wF.sub.v) is used to coat the pad layer 130 and the first passivation layer 120 by spin coating, and then the coated layer is baked at a low temperature, for example, at a temperature of 150 degrees Celsius to 400 degrees Celsius, for example, 150 degrees Celsius to 200 degrees Celsius. The spin-coating solution is coated on the pad layer 130 and the first passivation layer 120 to form the spin-coated glass layer 140 at a low temperature.

(8) According to an embodiment of the present invention, the SOG layer 140 fills the recessed region S, and thus has a flat top surface 140a. According to an embodiment of the present invention, a partial top surface 140a of the SOG layer 140 is higher than the top surface 130a of the pad layer 130. According to an embodiment of the present invention, the SOG layer 140 is in direct contact with the sidewall 130s and the top surface 130a of the pad layer 130.

(9) According to an embodiment of the present invention, next, as shown in FIG. 3, a second passivation layer 150 is formed on the SOG layer 140. According to an embodiment of the present invention, the second passivation layer 150 may be a silicon nitride layer. According to an embodiment of the present invention, the second passivation layer 150 is in direct contact with the SOG layer 140. According to an embodiment of the present invention, the second passivation layer 150 may be formed using a PECVD process.

(10) One advantage of the present invention is that the SOG layer 140 covering the pad layer 130 and the first passivation layer 120 is formed by spin-coating and low-temperature baking, which can improve the influence of the thermal expansion effect and obtain a good step coverage, thereby strengthening the regions with weaker strength between the pad layers 130. The second passivation layer 150 with higher hardness is then deposited as a protective layer. The present invention can effectively solve the problem of cracking of the passivation layer.

(11) Structurally, as shown in FIG. 3, the semiconductor structure 1 includes: a substrate 100; a top metal layer 112 disposed in the top IMD layer 110 on the substrate 100; a first passivation layer 120 covering the top metal layer 112 and the top IMD layer 110; a pad layer 130 disposed on the first passivation layer 120 and electrically connected to the top metal layer 112; a spin-on glass (SOG) layer 140 covering the pad layer 130 and the first passivation layer 120; and a second passivation layer 150 disposed on the SOG layer 140.

(12) According to an embodiment of the present invention, the pad layer 130 is an aluminum pad layer.

(13) According to an embodiment of the present invention, the top metal layer 112 is a copper layer.

(14) According to an embodiment of the present invention, the SOG layer 140 has a flat top surface 140a.

(15) According to an embodiment of the present invention, a partial top surface 140a of the SOG layer 140 is higher than the top surface 130a of the pad layer 130.

(16) According to the embodiment of the present invention, the SOG layer 140 is in direct contact with the sidewall 130s and the top surface 130a of the pad layer 130.

(17) According to an embodiment of the present invention, the first passivation layer 120 is a silicon oxide layer.

(18) According to an embodiment of the present invention, the second passivation layer 150 is a silicon nitride layer.

(19) According to the embodiment of the present invention, the second passivation layer 150 is in direct contact with the SOG layer 140.

(20) According to an embodiment of the present invention, the semiconductor structure 1 further includes: a via plug 124 located in the first passivation layer 120 for electrically connecting the pad layer 130 with the top metal layer 112; and a liner layer 126 located between the via plug 124 and the first passivation layer 120.

(21) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.