A semiconductor device includes: a heat dissipation base; a case including an outer peripheral wall that has an inner surface facing an inside of the case and a wiring terminal provided integrally with the outer peripheral wall, the wiring terminal having an inner end portion, which is on one end of the wiring terminal and is exposed to the inside of the case from the inner surface of the outer peripheral wall; a sealing member sealing the inside of the case; and an adhesion member embedded in the inner surface of the case and having an adhesion surface exposed from the inner surface, the adhesion member and the heat dissipation base being on different sides of the inner end portion. The adhesion surface has higher adhesion to the sealing member than the outer peripheral wall.

A first semiconductor chip has a first surface in contact with a first circuit board and a second surface on which a second conductor is provided. A second semiconductor chip has a third surface in contact with a second circuit board and a fourth surface on which a third conductor is provided. A first pillar has a fifth surface in contact with the first circuit board. A second circuit board is in contact with a surface of a second conductor, a surface of a third conductor, and the first pillar. A plurality of insulating pillars extends in a direction connecting the first and second circuit boards and are in contact with the first and second circuit boards. A sealing body surrounds the first and second semiconductor chips, the first pillar, and the insulating pillars, and includes.

Provided is a semiconductor package including a package substrate including a substrate pad, a first chip stacked structure including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked along a first direction on the first base chip, a second chip stacked structure including a second base chip offset-stacked along the first direction on an upper surface of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked along the first direction on the second base chip, a bonding wire, and a first support mounted on the package substrate to be spaced apart from the first chip stacked structure in the first direction and supporting the second chip stacked structure, wherein the first support supports the second chip stacked structure by supporting a lower surface of the second base chip.

A method of manufacturing a semiconductor package includes mounting a first semiconductor die over a package substrate, forming a first connector to electrically connect the first semiconductor die to the package substrate, offset-stacking a second semiconductor die over the first semiconductor die in a first direction, offset-stacking a third semiconductor die on the second semiconductor die in a second direction, offset-stacking a fourth semiconductor die on the third semiconductor die in the second direction, forming a second connector to electrically connect the second semiconductor die to the package substrate, forming a third connector to electrically connect the third semiconductor die to the package substrate, and forming a fourth connector to electrically connect the fourth semiconductor die to the package substrate.

According to one embodiment, a semiconductor device includes a wiring substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface. A first electrode is on the first surface. A semiconductor element is on the wiring substrate and electrically connected to the first electrode. A resin layer covers the semiconductor element and the first surface from a first direction orthogonal to the first surface. A portion of the resin layer contacts the side surface of the wiring substrate from a second direction parallel to the first surface. The resin layer has an outside side surface that is substantially parallel to the first direction.

A semiconductor package includes: a lower substrate including a lower wiring layer; an upper substrate disposed on the lower substrate and including an upper wiring layer and a cavity; an adhesive layer disposed in the cavity; a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein connection pads are disposed on the first surface of the semiconductor chip and are electrically connected to the lower wiring layer, and wherein the second surface of the semiconductor chip is attached to the adhesive layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer; an encapsulant at least partially surrounding at least a portion of each of the semiconductor chip and the connection structure; and connection bumps electrically connected to the lower wiring layer.

A package structure is provided. The package structure includes a substrate, a first electronic component, an encapsulant, and a protective element. The first electronic component is over the substrate. The encapsulant is over the substrate and defines a cavity that exposes the first electronic component. The protective element covers the first electronic component. A lateral surface of the protective element is substantially aligned with a lateral surface of the encapsulant.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

A semiconductor package according to an embodiment of the present disclosure includes: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; at least one heat dissipation wire connected to the semiconductor chip; and an encapsulant on at least a portion of each of the semiconductor chip and the heat dissipation wire. The heat dissipation wire is exposed to one side surface of side surfaces of the encapsulant.

An embodiment provides a semiconductor package including a package substrate including substrate pads, and a chip stack including a plurality of semiconductor chips stacked on the package substrate, wherein the plurality of semiconductor chips include first and second semiconductor chips having the same size and shape device region, the first and second semiconductor chips include first and second chip pad regions protruding from different regions of a first side of the device region, respectively, and each chip pad being connected to a substrate pad by a wire, and the first and second semiconductor chips are stacked such that the first and second chip pad regions face in the same horizontal direction and do not overlap each other in a stacking direction.