A semiconductor memory device includes first and second memory cell arrays. The first array includes a first semiconductor portion, extending in a first direction, on which a first memory cell and a first select transistor are formed, a first word line connected to the first cell, a first select gate line connected to the first transistor, and a first bit line connected to the first semiconductor portion. The second array includes a second semiconductor portion, extending along the first direction, on which a second memory cell and a second select transistor are formed, a second word line connected to the second cell, a second select gate line connected to the second transistor, and a second bit line connected to the second semiconductor portion. The first and second word lines are electrically connected, but the first and second select gate lines are not electrically connected.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

A three-dimensional (3D) laminated chip that includes a first semiconductor chip including a first through electrode disposed therein. A second semiconductor chip is arranged horizontally adjacent to the first semiconductor chip. A third semiconductor chip is arranged on the first semiconductor chip and the second semiconductor chip. A size of the third semiconductor chip is greater than a size of the first semiconductor chip.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.

A method for manufacturing a semiconductor bonding structure is provided. The method includes forming a first semiconductor structure, forming a second semiconductor structure and hybrid bonding the first semiconductor structure and the second semiconductor structure. The step of forming the first semiconductor structure includes introducing boron into a first substrate to form an doped region in the first substrate, forming a first dielectric layer above the first substrate, and forming a first conductive pad in the first dielectric layer. The step of forming a second semiconductor structure includes forming a second dielectric layer above a second substrate, and forming a second conductive pad in the second dielectric layer. The first conductive pad is attached to the second conductive pad. The first dielectric layer is attached to the second dielectric layer.

A memory device is provided. The memory device includes: a memory cell array including a first string provided in a first layer and a second string provided in a second layer stacked on the first layer; a page buffer circuit including a first page buffer corresponding to the first string of the first layer and a second page buffer corresponding to the second string of the second layer; and a control logic circuit configured to control the first page buffer and the second page buffer independently, in a core operation.

An image sensor is provided. The image sensor includes a first semiconductor structure with photodiodes provided in a first semiconductor substrate, a first interconnection structure below the first semiconductor substrate, first bonding structures below the first interconnection structure and connected to the first interconnection structure, first shielding structures between the first bonding structures, and a first bonding insulating film surrounding lower regions of the first bonding structures and lower regions of the first shielding structures; and a second semiconductor structure a second interconnection structure provided in a second semiconductor substrate, second bonding structures contacting the first bonding structures on the second interconnection structure and connected to the second interconnection structure, second shielding structures between the second bonding structures and contacting the first shielding structures, and a second bonding insulating film surrounding upper regions of the second bonding structures and upper regions of the second shielding structures.

An example semiconductor memory device may include a first conductive line extending in a first direction perpendicular to a substrate, a first gate electrode extending in a second direction, crossing the first direction, on the substrate, a first semiconductor pattern extending from the first conductive line to the first gate electrode, a second gate electrode spaced apart from the first gate electrode on the substrate and extending in the second direction, and a contact extending in the first direction and electrically connected with the first gate electrode and the second gate electrode.

A semiconductor device includes a substrate, a first contact electrode connected to the substrate, a second contact electrode separated from the first electrode and connected to the substrate, a gate electrode facing the substrate between the first and second contact electrodes, a third contact electrode on the gate electrode, a first electrode member facing the substrate between the first contact electrode and the gate electrode, and a second electrode member facing the substrate between the second contact electrode and the gate electrode. The gate electrode contains a first conductivity type impurity. The first and second electrode members contain the first conductivity type impurity or a second conductivity type impurity. A concentration of the first or the second conductivity type impurity in the first and second electrode members is lower than a concentration of the first conductivity type impurity in the gate electrode.