A semiconductor device includes a cell structure including gate electrodes and mold insulating layers alternately stacked one by one in a vertical direction, a channel structure extending in the vertical direction through the gate electrodes and the insulating layers, wherein a first end portion of the channel structure protrudes upward from an uppermost mold insulating layer, and a common source layer connected to the first end portion of the channel structure and located on the uppermost mold insulating layer. The uppermost mold insulating layer includes a first low-refractive-index layer on a lower surface of the common source layer, a high-refractive-index layer on a lower surface of the first low-refractive-index layer, and a second low-refractive-index layer on a lower surface of the high-refractive-index layer.

A semiconductor package is provided. The semiconductor package includes a first semiconductor chip including a device region and a dummy region surrounding the device region in a two-dimensional perspective, second semiconductor chips on an upper surface of the device region of the first semiconductor chip, and a molding layer on the first semiconductor chip and covering the second semiconductor chips, wherein each of the second semiconductor chips includes a second semiconductor substrate, a second lower pad on a lower surface of the second semiconductor substrate, and a second upper pad in an upper portion of the second semiconductor substrate, and a volume of the second lower pad is greater than a volume of the second upper pad.

A semiconductor device includes a substrate, first and second semiconductor layers arranged in this order apart from each other in a first direction; first wiring layers arranged apart from each other in the first direction between the substrate and the first semiconductor layer and including a first layer; second wiring layers arranged apart from each other in the first direction between the first and second semiconductor layers and including a second layer; first and second memory pillars extending in the first direction and having portions that intersect the respective first and second wiring layers and function as memory cells; and a first contact extending in the first direction to intersect with the first wiring layers, being in contact with the first layer, being insulated from the first wiring layers excluding the first layer and the first semiconductor layer, and electrically connecting the substrate and the second layer.

A semiconductor device may include high-integrated memory cells, and a method for fabricating the semiconductor device may include forming a plurality of preliminary nano sheets disposed with first horizontal gaps therebetween over a substrate, forming a spacer layer surrounding portions of the preliminary nano sheets and defines second horizontal gaps between the preliminary nano sheets, forming gap-fill layers that fill the second horizontal gaps of the spacer layer, forming inter-cell dielectric layers on the gap-fill layers and the spacer layer, horizontally recessing the gap-fill layers and the spacer layer and forming a linear surrounding recess, and forming a conductive line horizontally extending while surrounding portions of the preliminary nano sheets in the linear surrounding recess.

A display panel includes a circuit substrate, pixel structures and a molding layer. The circuit substrate has first pad structures and second pad structures. The pixel structures are disposed above a display region of the circuit substrate. Each of at least a portion of the pixel structures includes a first light emitting diode, a first conductive block, and a first conductive connection structure. The first light emitting diode is disposed on a corresponding first pad structure. The first conductive block is disposed on a corresponding second pad structure. The first conductive connection structure electrically connects the first light emitting diode to the first conductive block. The molding layer is located above the circuit substrate and surrounds the first light emitting diode and the first conductive block. The first conductive connection structure is located on the molding layer.

A semiconductor package includes at least a first die. The first die includes an internal circuit disposed on a substrate, an electrostatic discharge (ESD) protection circuit disposed on the substrate but laterally spaced from the internal circuit and including a first charge dissipation element, and a first Silicon Controlled Rectifier (SCR) laterally adjacent to and spaced from the first charge dissipation element.

A device comprising a substrate; and a stack of chips coupled to the substrate, wherein the stack of chips comprises: a logic chip; and a first memory chip coupled to the logic chip, wherein the first memory chip comprises a first die substrate; a first plurality of memory cells; and a first plurality of memory cell structures located along at least one edge of the first memory chip.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

An image sensor includes a first substrate having a first surface and a second surface opposite to the first surface, and including a plurality of pixel region groups, each of the pixel region groups including a plurality of pixel regions, the pixel regions oriented in a first and second directions parallel to the first surface, the second direction intersecting the first direction; first bonding pads on the first surface and the pixel region groups; first shield conductive patterns on the first surface, on each of boundaries of the pixel region groups parallel to the first direction, and oriented in matrix form along the first direction and second direction, columns of the matrix apart from each other; and a first pickup region in at least one of the pixel regions, wherein each of the first shield conductive patterns is electrically connected to the first pickup region in a corresponding pixel region.