A semiconductor device includes: a lower structure; a horizontal conductive line which is oriented horizontally over the lower structure; a data storage element which is disposed over the lower structure to be spaced from the horizontal conductive line; a vertical conductive line which is vertically oriented between the horizontal conductive line and the data storage element; a horizontal layer which is oriented horizontally between the horizontal conductive line and the data storage element, and including a recessed side which is disposed adjacent to the vertical conductive line; and a body contact portion oriented which is vertically oriented by penetrating the horizontal layer.

One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.

A semiconductor package is provided. The semiconductor package includes: an interposer; a System on Integrated Chips (SoIC) die stack bonded to a top surface of the interposer, the SoIC die stack comprising two or more dies bonded together; and a plurality of chips bonded to the top surface of the interposer. A first lateral distance, in a first direction, between a first boundary of the SoIC die stack and a boundary of a neighboring chip among the plurality of chips is larger than a first threshold distance.

A semiconductor device assembly including a first semiconductor die having a first dielectric region and a first bond pad that are disposed on a first side of the first semiconductor die; a second semiconductor die having a second dielectric region and a second bond pad that are disposed on a second side of the second semiconductor die; and a hybrid bonding interface between the first side of the first semiconductor die and the second side of the second semiconductor die, the hybrid bonding interface including a gap free metal-metal bonding region between the first and the second bond pads and a gap free dielectric-dielectric bonding region between the first and the second dielectric regions, wherein the dielectric-dielectric bonding region includes a nitrogen gradient with a concentration that increases with proximity to the metal-metal bonding region.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor slab with a channel region and a first surface. A first gate structure surrounds the channel region in the first GAA FET, and a second gate structure surrounds the channel region in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some examples, a first crystal structure of the 3D semiconductor slab in the first GAA FET has a first orientation, and a second crystal structure of the 3D semiconductor slab in the second GAA FET has a different orientation for improved carrier mobility.

A bonded structure is disclosed. The bonded structure can include a substrate. The bonded structure can include a first memory unit disposed on the substrate. The first memory unit can have a first stack of memory dies and a first logic controller disposed on the first stack. The first logic controller can manage data communicated to or from the first stack of memory dies. The bonded structure can also include a processor die hybrid bonded to the first memory unit along a bonding interface and a vertical interconnect connecting the substrate to the processor die. The bonded structure can further include a second memory unit disposed on the substrate. The second memory unit can include a second stack of memory dies and a second logic controller disposed on the second stack. The second logic controller can manage data communicated to or from the second stack of memory dies.

A chip structure including: a photonic integrated circuit (PIC) chip; an electronic integrated circuit (EIC) chip disposed on the PIC chip; and an optical block disposed on the PIC chip, spaced apart from the EIC chip in a horizontal direction, and configured to transfer optical signals to the PIC chip.

A memory device includes a substrate, a gate line contact electrically connected to a gate line selected from among the gate lines, a conductive wiring structure connected to the gate line contact, and bonding pads arranged on the conductive wiring structure. The bonding pads include a first bonding pad, a second bonding pad, a third bonding pad apart from the first bonding pad in the first horizontal direction, and a fourth bonding pad apart from the first bonding pad in a second horizontal direction perpendicular to the first horizontal direction. The conductive wiring structure electrically connects the first bonding pad and the second bonding pad to the gate line contact, and the second bonding pad is arranged diagonally between the first horizontal direction and the second horizontal direction with respect to the first bonding pad.

A method for automatically generating chip identifier for semiconductor dies in a stacked structure is provided. The method includes the following steps: obtaining a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die include a first identifier generation circuit and a second identifier generation circuit, respectively; forming a stacked structure by stacking the second semiconductor die on the first semiconductor die, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit; and generating a first chip identifier and a second chip identifier for the first semiconductor die and the second semiconductor die by the first identifier generation circuit and the second identifier generation circuit, respectively. The second chip identifier is generated using the first chip identifier and an auxiliary input signal.