An output matching circuit includes a transformer having one end electrically connected to an output terminal of a power amplifier element that amplifies an input signal and another end electrically connected to a terminal connected to a load, and converting an impedance of the terminal connected to the load to an impedance higher than an impedance of the output terminal, a first filter circuit that attenuates a signal within a first frequency band higher than a transmission frequency band of the input signal, and a second filter circuit that attenuates a signal within a second frequency band higher than the first frequency band.

Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate between and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET) including a source region, a drain region, a body region coupled to a body resistor, and a gate region coupled to a gate resistor. The RFIC also includes a dynamic bias control circuit. The dynamic bias control circuit includes at least one transistor coupled to the body region of the switch FET through the body resistor and coupled to the gate region of the switch FET through the gate resistor. The at least one transistor is an RF silicon on insulator (SOI) device. The dynamic bias control circuit also includes a capacitor coupled to the gate resistor and the body resistor and coupled in parallel with each transistor in the dynamic bias control circuit.

Design and construction of high interconnection density, minimal loss I/O channels comprising embedded passive networks that preserve signal integrity at signaling frequencies above 1 GHz, preferably above 10 GHz, to improve memory-processor bandwidths.

A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.

Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

A method of fabricating an electronic device includes forming a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.