A semiconductor device includes a semiconductor die including a central region and an outer region surrounding the central region, a semiconductor integrated circuit across a plurality of sub regions of the central region, an outer crack detection structure in the outer region along an edge of the outer region and divided into a plurality of outer conduction segments, a central crack detection structure crossing the central region and divided into a plurality of central conduction segments, a plurality of first path selection circuits each connected to at least one of the plurality of outer conduction segments and at least one of the plurality of central conduction segments, and a second path selection circuit connected between the plurality of central conduction segments.

An inspection pattern capable of performing wafer-level automatic inspection using a cantilever-type probe card is provided. An inspection pattern according to one embodiment of the present disclosure includes: a Cu pillar pad formed on a semiconductor substrate; a Cu pillar formed on the Cu pillar pad; and an inspection pad formed on the semiconductor substrate, electrically coupled adjacent to or proximate to the Cu pillar pad, and configured to provide a region that a cantilever-type probe comes in contact with during wafer-level automatic inspection.

A memory wafer is described. The memory wafer includes memory dies on the memory wafer. Additionally, the memory wafer includes wire connections at least partially within one of the memory dies. The wire connections are configured to couple to memory test and repair pads along at least one scribe line between the one of the memory dies and adjacent memory dies.

A device comprising a substrate; and a stack of chips coupled to the substrate, wherein the stack of chips comprises: a logic chip; and a first memory chip coupled to the logic chip, wherein the first memory chip comprises a first die substrate; a first plurality of memory cells; and a first plurality of memory cell structures located along at least one edge of the first memory chip.

A semiconductor device including a hydrogen test pattern for testing the influence of hydrogen on an insulation layer is disclosed. The semiconductor device includes a target insulation layer shared by a transistor pattern disposed in a first region and a test pattern disposed in a second region. The test pattern includes detection interconnect elements disposed within the target insulation layer, and outputs a test current corresponding to a test voltage provided through the detection interconnect elements.

A device may include a contactor pad having a first side and a second side. A device may include an opening extending through the contactor pad from the first side to the second side, the opening being configured to receive at least a portion of a socket assembly associated with automated test equipment (ATE) for a semiconductor device. A device may include retaining members disposed on the first side and adjacent to respective edges of the opening, the retaining members being configured to removably secure the socket assembly in the opening.

A semiconductor memory device includes bitlines, a memory cell array, a plate electrode structure, a bitline shielding structure, and a conductive path. The memory cell array includes memory cells connected to the bitlines. The plurality of memory cells are arranged in the first direction and the second direction. Each memory cell includes a cell transistor and a cell capacitor that are arranged in a third direction perpendicular to the surface of the semiconductor substrate. The plate electrode structure forms a common electrode of cell capacitors included in the plurality of memory cells. The bitline shielding structure is disposed between the plurality of bitlines to block electrical interference between the plurality of bitlines. The capacitance-connection conductive path electrically connects the plate electrode structure and the bitline shielding structure.

Provided is a semiconductor element including a semiconductor substrate; a semiconductor layer laminated to the semiconductor substrate, and having a circuit formed within the semiconductor layer; a conductive layer disposed on an opposite side of the semiconductor layer from the semiconductor substrate and including a part electrically connected to the circuit; and a conductive portion disposed between the semiconductor layer and the conductive layer, and electrically connected to the conductive layer. The conductive layer includes a check pattern not electrically connected to the circuit, and the conductive portion includes a superimposition portion superimposed on the check pattern as viewed in a thickness direction of the semiconductor substrate.

An electronic system includes a first device and a second device bonded to the first device. The first device includes: a semiconductor substrate with an opening; a stack having metal layers and conductive vias; and a conductive layer including aluminum having a first face in contact with the stack and a second face, opposite the first face, that is partially exposed through the opening. The metal layers and the conductive vias of the stack are made of a conductive material different from aluminum.

A semiconductor test structure includes a substrate, a first gate structure and a second gate structure, a first conductive layer and an air gap. The first gate structure and the second gate structure are stacked on the substrate along a first direction, extend along a second direction and are spaced apart from each other along a third direction. The first conductive layer is stacked on the substrate and includes a first electrode and a second electrode. The first electrode extends along the second direction, and at least a portion of the second electrode extends along the second direction. A region of the air gap projected on the substrate along the first direction is between regions of the first gate structure and the second gate structure projected on the substrate along the first direction.