A wafer test probe includes a pillar, a conductive line isolated from and extending through the pillar, a probe tip forming an opening, and a first conductive coating isolated from the pillar to coat the probe tip at least at the opening. The probe time includes blade features disposed in electrical contact with the conductive line via the first conductive coating. The blade features terminate at the opening and are configured to conductively penetrate a solder bump. A second conductive coating is disposed over the first conductive coating to coat the blade features.

A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

An electronic system comprising an integrated circuit, including a semiconductor substrate, an interconnection portion located above the substrate and having metal levels and vias and contacts levels embedded in an electrically-insulating region as well as contact pads located at the last metal level of the interconnection portion, and a detection system configured to detect a possible presence of at least one type of structural defects within at least one area of the interconnection portion located at least beneath a contact pad.

Some embodiments relate to an integrated device, including: a first interconnect structure on a first substrate; a first central bond pad coupled to the first interconnect structure; a first peripheral bond pad on a first side of the first central bond pad separated by a first distance; a second peripheral bond pad on a second side of the first central bond pad and separated by a second distance substantially equal to the first distance; a second interconnect structure on a second substrate; a first overlying bond pad coupled to the second interconnect structure and bonded to the first central bond pad; and a plurality of exposed bond pads respectively coupled to the first central bond pad, the first peripheral bond pad, the second peripheral bond pad, and the first overlying bond pad, wherein the plurality of exposed bond pads extend past outer sidewalls of the second substrate.

A method of manufacturing a semiconductor device is provided, the method including: forming an insulating film on a semiconductor substrate; selectively removing the insulating film; forming a metal film on the semiconductor substrate by leaving a damage layer of a surface of the semiconductor substrate, the damage layer being generated when the insulating film is selectively removed; forming an electrode by selectively removing the metal film; and forming polyimide on the electrode. The damage layer of the surface of the semiconductor substrate, which is generated when the insulating film is selectively removed, may be selectively removed.

An array substrate includes a base substrate, a first conductive layer and a second conductive layer. The first conductive layer is provided on a side of the base substrate and includes a first conductive portion. The second conductive layer is provided on a side of the first conductive layer away from the base substrate and includes a second conductive portion. The projection of at least part of the second conductive portion on the base substrate and the projection of the first conductive portion on the base substrate do not overlap. The first conductive portion is provided with an opening area, and a projection of at least part of the second conductive portion on the base substrate is located in an area enclosed by a projection of the opening area.

A manufacturing method for a semiconductor device includes: obtaining a pre-processed semiconductor structure, wherein the pre-processed semiconductor structure comprises a metal layer (103) having a first exposed surface (1032), and the first exposed surface (1032) of the metal layer has a protrusion portion (1031); arranging a protective layer (104) on the first exposed surface (1032) of the metal layer, wherein the protective layer (104) at least covers part of the metal layer (103) that excludes the protrusion portion (1031); removing the protrusion portion (1031) to form on the metal layer (103) a second exposed surface (1033) of the metal layer (103); and forming a dielectric layer (105) on an area where the first exposed surface (1032) is located, wherein the dielectric layer (105) completely covers the area where the first exposed surface (1032) is located.

An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Semiconductor structures and methods for manufacturing and testing semiconductor structures are provided. The semiconductor structures include an integrated circuit formed in a semiconductor substrate, a seal ring on at least a first side of the semiconductor substrate and surrounding a perimeter of the integrated circuit, an input element, an output element, and a backside metal die damage ring (BMDDR) disposed on the first side of the semiconductor substrate, extending through the semiconductor substrate, and disposed on a second side of the semiconductor substrate, the BMDDR disposed between the integrated circuit and the seal ring, the BMDDR at least partially surrounding the perimeter of the integrated circuit, the BMDDR coupled to and forming an electrical circuit between the input element and the output element.

A semiconductor device includes a bottom die and a top die. The includes a first test pad set, a second test pad set, a first bottom BPM set electrically connected with the first test pad set, and a second bottom BPM set electrically connected with the second test pad set. The top die includes a first top BPM set bonding to the first bottom BPM set, and a second top BPM set bonding to the second bottom BPM set. The first test pad set has a test pad area, the first bottom BPM set has a first bottom BPM area, and the second bottom BPM set has a second bottom BPM area. The test pad area is greater than the first bottom BPM area and the second bottom BPM area, and the first bottom BPM area is equal to or less than the second bottom BPM area.