A method of manufacturing a high electron mobility transistor (HEMT) structure is disclosed. By controlling a passivation layer and a barrier layer to uninterruptedly grow in the same growth chamber, defects of the passivation layer generated in the growth process due to a drastic change in temperature, pressure, or atmosphere or degrading a quality of an interface between the passivation layer and the barrier layer could be avoided, thereby providing the passivation layer with a good quality and the interface between the passivation layer and the barrier layer with a good quality, so that the objective of improving the performance of the HEMT structure could be achieved.

Methods of depositing silicon-containing films by plasma-enhanced vapor deposition, e.g., plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD), are disclosed. Exemplary methods include exposing a substrate in a processing system to a silicon-containing precursor; exposing the substrate to an oxygen-containing reagent; and exposing the substrate to a plasma of an inert gas.

A semiconductor processing device is disclosed. The device can include a reactor and a solid source vessel configured to supply a vaporized solid reactant to the reactor. A process control chamber can be disposed between the solid source vessel and the reactor. The device can include a valve upstream of the process control chamber. A control system can be configured to control operation of the valve based at least in part on feedback of measured pressure in the process control chamber.

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

A method of fabricating a semiconductor device includes providing a GaN substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate, the heterojunction supporting a 2-dimensional electron gas (2DEG) channel in the GaN substrate. A composite surface passivation layer is formed over a top surface of the epitaxial layer, wherein the composite surface passivation layer comprises a first passivation layer portion formed proximate to a first region of the GaN device and a second passivation layer portion formed proximate to a second region of the GaN device. The first and second passivation layer portions are disposed laterally adjacent to each other over the epitaxial layer, wherein the first passivation layer portion is formed in a first process and the second passivation layer portion is formed in a second process.

A technique includes: (a) a pair of injectors each supplying a film formation gas toward a substrate; (b) a pair of tanks connected to the pair of injectors respectively and accumulating the gas; (c) a pair of opening and closing valves controlling fluid communication of the gas between the pair of injectors and the pair of tanks in a corresponding manner, respectively; (d) a pair of pressure gauges measuring internal pressures of the pair of tanks, respectively, during accumulation of the gas; (e) a pair of flow rate limiters supplying the gas to the pair of tanks at a set flow rate set in advance to form a standard accumulation amount as a target amount of the gas, respectively; and (f) a controller capable of performing correcting the set flow rate so as to approach the standard accumulation amount.

There is provided a technique that includes: (a) supplying a precursor to a substrate; (b) supplying a reactant to the substrate; (c) supplying a regulating agent, which regulates an amount of at least one selected from the group of a molecule of the precursor and a molecule of the reactant adsorbed on the substrate, to the substrate; (d) performing a process in which at least one selected from the group of (a) and (b) overlaps (c); and (e) after (d), performing (a) or (b) which overlaps (c) in (d), independently of (c).

Semiconductor devices including dual surface passivation layers are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, a drain access region, and a source access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate electrode is disposed in the gate region of the semiconductor substrate, where the gate electrode includes an asymmetrical source-side field plate (e.g., including a single-step profile) extending over at least a portion of the source access region of the semiconductor substrate.

A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO.sub.2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.