A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.

The disclosure discloses a planar device, in a formation region of the planar device, the first and second semiconductor epitaxial layers on the semiconductor substrate have a patterned structure including: both the second semiconductor epitaxial layer and the first semiconductor epitaxial layer in the source-drain formation region being removed, and a first trench being formed. The first trench is filled with a first dielectric layer. A void structure is formed in the gate region after the first semiconductor epitaxial layer is removed. A third semiconductor epitaxial layer is formed on the top surface and an exposed side surface of the second semiconductor epitaxial layer, and constitutes a top epitaxial layer together with the second semiconductor epitaxial layer. A gate structure is formed on a top surface of the top epitaxial layer at the top of the void structure. The disclosure also discloses a method for manufacturing a planar device.

The present disclosure relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device, according to one embodiment, may comprise a gap-fill step of burying a gap-fill oxide in trenches formed on a substrate, so as to form a gap-fill oxide film. In one embodiment, the gap-fill step can comprise a high pressure oxidation (HPO) step. According to embodiments, a semiconductor device with electrical properties superior to those of a conventional semiconductor device can be manufactured.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a GaN heterojunction structure disposed on a substrate. The GaN heterojunction structure includes a barrier layer disposed on a GaN layer. The semiconductor device further includes a source contact, a drain contact, and a gate electrode. The gate electrode is disposed above the GaN heterojunction structure and between the source contact and the drain contact. The semiconductor device still further includes a plurality of segments of dielectric material disposed on the barrier layer between the source contact and the drain contact.

A method of fabricating semiconducting tellurium (Te) nanomesh. The method includes the steps of preparing a substrate, vaporizing Te powders under a first temperature; and growing Te nanomesh on the substrate using the vaporized Te powders under a second temperature. The first temperature is higher than the second temperature. The rationally designed nanomesh exhibits exciting properties, such as micrometer-level patterning capacity, excellent field-effect hole mobility, fast photoresponse in the optical communication region, and controllable electronic structure of the mixed-dimensional heterojunctions.

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Systems and methods for reducing obstructions in an exhaust line of a sub-atmospheric chemical vapor deposition (SACVD) system are disclosed. Such obstruction may occur due to the reaction of a silicon precursor with ozone, which forms solid particles in the exhaust line. A catalytic apparatus is provided which catalyzes the decomposition of ozone (O.sub.3) to oxygen (O.sub.2). Due to the lower reactivity of O.sub.2, the formation of solid particles is reduced.