An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. The width of the lower conductive section on a first boundary between the lower and upper conductive sections in the first direction is greater than the width of the upper conductive section on the first boundary in the first direction and the width of the second conductive pattern on a second boundary between the contact plug and the second conductive pattern in the first direction.

There is provided a technique that includes: (a) supplying a silicon- and ligand-containing gas to a substrate having a surface on a first base and second base are exposed to adsorb silicon contained in the silicon- and ligand-containing gas on a surface of one of the first and second base; (b) supplying a fluorine-containing gas to the substrate after the silicon is absorbed, to cause the silicon to react with the fluorine-containing gas to modify the surface to be F-terminated; and (c) supplying a film-forming gas to the substrate after the surface is modified, to thereby form a film on a surface of the other of the first base and the second base, which is different from the one of the first base and the second base.

Methods and associated devices including the fabrication of a semiconductor structure that provides a silicon-on-insulator substrate. The semiconductor structure may be formed by providing a base substrate, forming a sacrificial layer over the base structure, and forming a semiconductor layer over the sacrificial layer. The sacrificial layer is removed to form a void that is filled with oxide. The semiconductor structure includes a dielectric support feature extending through the semiconductor and oxide layers and/or a portion of the oxide layer extends to the surface of the semiconductor layer.

A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

An amorphous silicon layer or amorphous boron layer can be deposited on a substrate using one or more silicon or boron-containing precursors, respectively. Radical species are provided from a plasma source or from a controlled reaction chamber atmosphere to convert the amorphous silicon layer to a doped silicon layer with composition tunability. An initiation layer is deposited on one or more semiconductor device structures having a dielectric layer over an electrically conductive layer. The initiation layer may be conformally deposited by a CVD-based process and may comprises amorphous silicon, doped silicon, amorphous boron, or doped boron.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

A technique includes (a) preparing a substrate including a first region, which forms an outer surface of a recess and is adjacent to an opening of the recess and whose surface is terminated by a first termination, and a second region, which forms an inner surface of the recess and whose surface is terminated by the first termination; and (b) removing the first termination in the first region by exposing the substrate to a first processing solution containing a liquid that reacts with the first termination, so that a density of the first termination in the first region is smaller than a density of the first termination in the second region.

Various embodiments of methods are provided to control formation of self-assembled monolayers (SAMs) used in an area-selective deposition (ASD) process, and thus, prevent defects in the ASD process. In the disclosed embodiments, a SAM structure is formed via a spin-on process that includes: (a) a spin coating step for coating a surface of a semiconductor substrate with a liquid solution containing SAM-forming molecules, the semiconductor substrate having a target material and a non-target material exposed on the substrate surface, and (b) an anneal step for heat treating the semiconductor substrate to chemically bond the SAM-forming molecules to the non-target material exposed on the substrate surface. By controlling and/or varying process parameter(s) utilized during the anneal step, the embodiments disclosed herein improve the selectivity of the SAM structure to the non-target material and prevent defects from occurring when a film is subsequently deposited onto the target material.

It is possible to improve a productivity of substrate processing. There is provided a technique that includes: a process chamber; a source material supplier provided with containers storing the source material and capable of being replaced; a determination processor configured to check a remaining amount of the source material in a container currently in use among the containers during a substrate processing, and further configured to determine, from the remaining amount, whether or not a supply source of the source material needs to be switched from the container currently in use to a container in standby among the containers; and a controller configured to be capable of controlling the supply of the source material to be continuously performed by switching the container currently in use to the container in standby based on a determination result obtained by the determination processor.

A wafer support device according to an embodiment provides a wafer support device. The wafer support device has a support table and a wafer guide portion. The wafer guide portion includes a first chamfered portion and a second chamfered portion. The support table has a support surface that supports the wafer. The wafer guide portion has an annular shape that surrounds the circumference of the wafer supported on the support surface with the central axis extending in a normal direction of the support surface as a center. The first chamfered portion connects an inner circumferential surface and an upper surface of the wafer guide portion, and extends upward from the inner circumferential surface toward the outer circumferential side. The second chamfered portion connects an outer circumferential surface and the upper surface of the wafer guide portion, and extends upward from the outer circumferential surface toward the inner circumferential side.