A method of manufacturing a high electron mobility transistor (HEMT) structure is disclosed. By controlling a passivation layer and a barrier layer to uninterruptedly grow in the same growth chamber, defects of the passivation layer generated in the growth process due to a drastic change in temperature, pressure, or atmosphere or degrading a quality of an interface between the passivation layer and the barrier layer could be avoided, thereby providing the passivation layer with a good quality and the interface between the passivation layer and the barrier layer with a good quality, so that the objective of improving the performance of the HEMT structure could be achieved.

Described herein is a technique capable of improving the controllability of a thickness of a film formed on a large surface area substrate having a surface area greater than a surface area of a bare substrate and improving the thickness uniformity between films formed on a plurality of large surface area substrates accommodated in a substrate loading region by reducing the influence of the surface area of the large surface area substrate and the number of the large surface area substrates due to a loading effect even when the plurality of large surface area substrates are batch-processed using a batch type processing furnace.

A method includes introducing a semiconductor-containing precursor gas into a reaction chamber through a gas passage; directing the semiconductor-containing precursor gas from the gas passage to a region over a shower plate, wherein the shower plate is above the gas passage and a wafer in the reaction chamber; guiding the semiconductor-containing precursor gas to flow through the shower plate; rotating the wafer; and epitaxially growing an epitaxy feature over the wafer by using the semiconductor-containing precursor gas to interact with the wafer when rotating the wafer.

A semiconductor processing device is disclosed. The device can include a reactor and a solid source vessel configured to supply a vaporized solid reactant to the reactor. A process control chamber can be disposed between the solid source vessel and the reactor. The device can include a valve upstream of the process control chamber. A control system can be configured to control operation of the valve based at least in part on feedback of measured pressure in the process control chamber.

The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

A reaction apparatus for depositing an epitaxial layer on a semiconductor structure. The reaction apparatus includes a first gas inlet for channeling a first process gas into the reaction chamber in a first direction. The reaction apparatus includes a second gas inlet for channeling a second process gas into the reaction chamber in a second direction. The first direction and second direction form an angle of between 45 and 75.

The present invention relates to a layer formation method and, more specifically, to a semiconductor device manufacturing method for forming a semiconductor device through a low-temperature process. The layer formation method according to an embodiment of the present invention is a method for manufacturing a semiconductor device which comprises a silicon substrate containing germanium (Ge) or a substrate on which a silicon layer containing germanium (Ge) is formed, and which comprises an undoped gallium nitride (GaN) layer, an N-type gallium nitride (GaN) layer, an active layer and a P-type gallium nitride (GaN) layer, wherein a step of forming at least one gallium nitride layer from among the undoped gallium nitride (GaN) layer, the N-type gallium nitride (GaN) layer, the active layer and the P-type gallium nitride (GaN) layer comprises the steps of: a) sequentially supplying a gallium (Ga) precursor and a nitrogen (N2) precursor at 500 C. or lower, thereby forming a gallium nitride (GaN) layer on the substrate; and b) exposing the gallium nitride (GaN) layer to a hydrogen-containing plasma, and steps a) and b) are repeated multiple times.

A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.

There are provided (a) heat-treating a substrate including a film containing a group 14 element at a first temperature; (b) heat-treating the substrate at a second temperature higher than the first temperature; and (c) exposing the substrate to a treatment agent containing at least one of O and H after performing (a) and before performing (b).

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.