According to one embodiment, a semiconductor device includes: a circuit board; a first semiconductor chip mounted on a face of the circuit board; a resin film covering the first semiconductor chip; and a second semiconductor chip having a chip area larger than a chip area of the first semiconductor chip, the second semiconductor chip being stuck to an upper face of the resin film and mounted on the circuit board. The resin film entirely fits within an inner region of a bottom face of the second semiconductor chip when viewed in a stacking direction of the first and second semiconductor chips.

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.

A double-sided liquid-cooling power module mounted with a plurality of power semiconductor devices, including a watertight housing and a power device package, the power device package including a lower ceramic substrate, a power semiconductor device, a copper saddle-shaped upper guide column, an upper ceramic substrate, a shunt support column, and a resin dielectric package, a bottom surface electrode of the power semiconductor device being correspondingly press-bonded with a silver thin film layer, a top surface electrode being press-bonded with an interfacial silver thin film layer; the power semiconductor device is encapsulated by the resin dielectric package; an electrical conduction loop is formed by press-bonding the power semiconductor device to the lower ceramic substrate via the silver thin film layer and press-bonding the copper saddle-shaped upper column to the power semiconductor device via the silver thin film layer; a double-sided heat dissipation effect is achieved with the watertight housing.

An integrated chip includes a first chip and a second chip bonded to the first chip. The first chip includes a first substrate, a first transistor along the first substrate, a first interconnect over the first transistor, and a first bonding pad over the first interconnect. The second chip includes a second substrate, a second transistor along the second substrate, a second interconnect under the second transistor, and a second bonding pad under the second interconnect. The second bonding pad is bonded to the first bonding pad. The first chip further includes a trench capacitor over the first interconnect and under the first bonding pad. The trench capacitor includes a bottom electrode, a top electrode, and an insulator layer between the bottom and top electrodes. The first bonding pad extends from the second bonding pad to the top electrode of the trench capacitor.

A semiconductor structure includes a first semiconductor chip and a second semiconductor chip stacking with the first semiconductor chip along a first direction. The first semiconductor chip includes a first memory structure including a first contact structure extending along a first direction, and a first periphery structure disposed on a first substrate, the first periphery structure in contact with the first memory structure and including a second contact structure extending along the first direction. The second semiconductor chip is bonded to the first semiconductor chip through a chip-to-chip bonding layer, and the first contact structure and the second contact structure are coupled through a first coupling layer.

A chip packaging structure and fabrication method are provided. The chip packaging structure includes: one or more dies stacked on a packaging substrate in a vertical direction; and a packaging body surrounding the one or more dies. The packaging body includes: a compound layer in direct contact with the one or more dies, where the compound layer includes a material having a reference strength and a reference modulus; a first layer adjacent to a top surface of the packaging body, where the first layer includes a material having a first strength and a first modulus, and the first strength being greater than the reference strength; and a second layer positioned between the first layer and the one or more dies along the vertical direction, where the second layer includes a material having a second strength and a second modulus, and the second modulus being less than the reference modulus.

A semiconductor memory device includes a stacked body including a plurality of conductive layers and insulating layers alternately stacked in a first direction; and a contact plug electrically connected to a corresponding one of the conductive layers and extending from a step surface of the corresponding conductive layer in the first direction to penetrate through a corresponding portion of the stacked body.

The present disclosure provides a three-dimensional stacking fan-out packaging device and a method for preparing a three-dimensional stacking fan-out packaging device, and relates to the field of chip packaging. In this device, the concave chip bonding area is defined by the pre-supported electrical connection frame; a plurality of first chips with functional surfaces towards the first direction and a plurality of second chips with functional surfaces towards the second direction are arranged in the chip bonding area; and the first stacking chip and the second stacking chip are arranged in a central symmetry or plane symmetry.