A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.

Embodiments disclosed herein include an apparatus that comprises a substrate, and the substrate includes glass. In an embodiment, an opening is provided through a thickness of the substrate, and a layer is along a sidewall of the opening. In an embodiment, the layer comprises a polymer and an electrical conductor that comprises carbon. In an embodiment, a via is provided in the opening, and the via is an electrically conductive material.

Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Substrates with spacers, including substrates with solder resist spacers, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate comprises a first surface, a solder resist layer disposed over at least a portion of the first surface, and a plurality of electrical contacts at the first surface of the substrate. Electrical contacts of the plurality are configured to be coupled to corresponding electrical contacts at a surface of an electronic device. The substrate further includes a solder resist spacer disposed on the solder resist layer. The solder resist spacer can have a height corresponding to a thickness of the electronic device. The solder resist spacer can be configured as a dam to limit bleed out of underfill laterally away from the plurality of electrical contacts along the first surface and toward the solder resist spacer.

Substrates with spacers, including substrates with solder resist spacers, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate comprises a first surface, a solder resist layer disposed over at least a portion of the first surface, and a plurality of electrical contacts at the first surface of the substrate. Electrical contacts of the plurality are configured to be coupled to corresponding electrical contacts at a surface of an electronic device. The substrate further includes a solder resist spacer disposed on the solder resist layer. The solder resist spacer can have a height corresponding to a thickness of the electronic device. The solder resist spacer can be configured as a dam to limit bleed out of underfill laterally away from the plurality of electrical contacts along the first surface and toward the solder resist spacer.

A semiconductor device includes a glass interposer having a set of through glass vias (TGVs). At least one of the set of TGVs is filled with a moisture diffusive material.

Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material. In an embodiment, a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, the apparatus may further comprise a layer surrounding a perimeter of the first substrate, the second substrate, and the third substrate, where the layer comprises a dielectric material, with a fourth edge of the layer that is substantially linear. In an embodiment, a frame surrounds and contacts the fourth edge of the layer.

A semiconductor package may include a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a conductive post on the first redistribution substrate and horizontally spaced apart from the first semiconductor chip, the conductive post having protruding portions formed on a side surface thereof, a first mold layer disposed on the first redistribution substrate and a side surface of the first semiconductor chip, and a first interface layer including a vertical portion between the first mold layer and the protruding portions of the conductive post and a horizontal portion extending from a lower end portion of the conductive post.

A semiconductor package may include: a first wiring structure including a first wiring pattern and a first wiring insulating layer surrounding the first wiring pattern; a first semiconductor chip above the first wiring structure; a second semiconductor chip above the first wiring structure and spaced apart from the first semiconductor chip in a horizontal direction; an adhesive layer including a first portion on an upper surface of the first semiconductor chip, and further including a second portion on an upper surface of the second semiconductor chip; a molding member on the first wiring structure and surrounding side surfaces of each of the first semiconductor chip, the second semiconductor chip, and the adhesive layer; and a heat dissipation member on an upper surface of each of the molding member and the adhesive layer.

3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.