A packaging apparatus and methodology for a glass core package that can replace a BGA pinout with a well material perforated with through-holes filled with LM and protected by a thin layer of a dielectric material. The glass package with liquid metal (LM) socketing is to attach to a LM-compatible socket; the LM-compatible socket can be soldered to a main board or printed circuit board (PCB).

The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).

A semiconductor device assembly comprises an RDL including an external surface with external contacts, an internal surface with internal contacts, and conductors coupling the internal contacts to the external contacts. The assembly further includes a device connection layer having a first surface with first contact pads, a second surface with second contact pads, first conductive structures electrically coupling each of the first contact pads to a corresponding second contact pad, and a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads. The assembly further includes stacks of semiconductor devices disposed between the RDL and the device connection layer, each stack in a cavity in a monolithic glass structure. The stacks electrically couple internal contacts to the first contact pads through TSVs in the stacks.

A described example includes: a passive component die mounted to a device side surface of a semiconductor device die, and extending away from the device side surface of the semiconductor device die; the semiconductor device die and the passive component die flip chip mounted to a device mounting surface of a package substrate including a cavity extending into the package substrate from the device mounting surface of the package substrate, the cavity in a position corresponding to the passive component die, the passive component die extending into the cavity of the package substrate, and the package substrate having terminals on a board side surface; and mold compound covering the semiconductor device die, the passive component die, and the device mounting surface of the package substrate, the mold compound forming the body of a microelectronic device package, the terminals of the package substrate forming terminals of the microelectronic device package.

Embodiments described herein may be related to apparatuses, processes, and techniques related to creating deep cavities within a substrate or at an edge of the substrate, by etching a cavity in the substrate to a first copper stop layer, removing the first copper stop layer, and then etching deeper into the cavity to a second copper stop layer. In embodiments this process may be repeated until the desired cavity depth is reached. Other embodiments may be described and/or claimed.

A semiconductor package includes a package substrate, a semiconductor chip, a plurality of conductive bumps and a molding compound. The package substrate has a first surface, a second surface opposite to the first surface, and at least one slot extending from the first surface to the second surface. The semiconductor chip is disposed on the package substrate and includes a chip circuit facing the slot of the package substrate. The conductive bumps are located between the package substrate and the semiconductor chip. The conductive bumps electrically connect the semiconductor chip to the package substrate. The molding compound encapsulates the semiconductor chip and the conductive bumps.

A semiconductor package includes a package substrate, a semiconductor chip, a plurality of conductive bumps and a molding compound. The package substrate has a first surface, a second surface opposite to the first surface, and at least one slot extending from the first surface to the second surface. The semiconductor chip is disposed on the package substrate and includes a chip circuit facing the slot of the package substrate. The conductive bumps are located between the package substrate and the semiconductor chip. The conductive bumps electrically connect the semiconductor chip to the package substrate. The molding compound encapsulates the semiconductor chip and the conductive bumps.

The invention provides a semiconductor structure, which comprises a chip comprising a substrate, wherein the substrate has a front surface and a back surface, and the front surface of the substrate comprises a circuit layer, the back surface of the substrate comprises a plurality of microstructures, and a thermal interface material located on the back surface of the substrate, and the thermal interface material contacts the microstructures directly.

The invention provides a semiconductor structure, which comprises a chip comprising a substrate, wherein the substrate has a front surface and a back surface, and the front surface of the substrate comprises a circuit layer, the back surface of the substrate comprises a plurality of microstructures, and a thermal interface material located on the back surface of the substrate, and the thermal interface material contacts the microstructures directly.

A substrate includes a ceramic tile and a three-dimensional (3D) conductive structure. The 3D conductive structure includes a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, and a block disposed above the planar base layer. The block is monolithically integrated with the planar base layer. A top surface of the block is configured as a die attach pad. The planar base layer has a base vertical thickness from the top surface of the ceramic tile to a top surface of the planar base layer. The block and the planar base layer have a combined vertical thickness from the top surface of the ceramic tile to a top surface of the block that is greater than the base vertical thickness.