A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

A method includes forming a first photoresist layer on a dielectric layer; performing a first light-exposure process on the first photoresist layer using a first photolithography mask, wherein during the first light-exposure process, a first region the first photoresist layer is blocked from being exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is exposed, wherein the second region encircles the first region and the third region encircles the second region; performing a second light-exposure process on the first photoresist layer using a second photolithography mask, wherein during the second light-exposure process, the first region of the first photoresist layer is exposed, the second region of the first photoresist layer is exposed, and the third region of the first photoresist layer is blocked from being exposed; and developing the first photoresist layer.

A method for processing a substrate includes receiving the substrate on a substrate holder disposed in a processing chamber, the substrate including a layer to be processed and a patterned mask disposed over the layer to be processed. The method further includes flowing a processing gas into the processing chamber, and replacing a material of the patterned mask with a metal of the processing gas to form a metal patterned mask occupying a same location as the patterned mask. And the method further includes etching, using the metal patterned mask as an etch mask, the layer to be processed to form a patterned layer, the patterned layer including feature openings.

An etch chamber includes a substrate support assembly for holding a base structure, and a showerhead comprising a plurality of gas delivery holes for delivering thionyl chloride. The etch chamber is configured to dry etch a target layer of the base structure at a sub-zero degree Celsius temperature using the thionyl chloride delivered by the showerhead in order to obtain a processed base structure. The processed base structure includes a plurality of features and a plurality of openings defined by an etch mask disposed on the target layer.

A method for manufacturing a metal fluoride-containing organic polymer film includes forming an organic polymer film on a base body. The method includes exposing the organic polymer film to an organometallic compound containing a first metal, thereby infiltrating the organic polymer film with the organometallic compound. The method includes exposing the organic polymer film infiltrated with the organometallic compound to hydrogen fluoride, thereby providing a fluoride of the first metal in the organic polymer film.

A method for forming a semiconductor device includes forming a first metal layer on top of an amorphous mask layer disposed over a substrate, forming a second metal layer that covers vertical sidewalls of openings in the amorphous mask layer, and etching a pattern in the substrate using the first metal layer and the second metal layer as an etch mask.

A method for etching a dielectric layer covering a top and a flank of a three-dimensional structure, this method including a first etching of the dielectric layer, including a first fluorine based compound, a second compound taken from SiwCl(2w+2) and SiwF(2w+2), oxygen, this first etching being carried out to form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and second etchings being repeated until removing the dielectric layer located on the flank of the structure. The second etching can be carried out by hydrogen-based plasma.

A method of manufacturing a semiconductor device may include sequentially forming a word line filling a word line trench of a substrate and a buried insulation layer on the word line, performing a first etching process of forming a logic active region contact hole extending to an inner portion of a logic active region of the substrate and a word line contact hole extending to an inner portion of the buried insulation layer, and performing a second etching process so that the word line contact hole extends to an inner portion of the word line. The first etching process may be performed using a first etching gas, which may include difluoromethane (CH.sub.2F.sub.2) and octafluorobutyne (C.sub.4F.sub.8) and where a ratio of difluoromethane to octafluorobutyne may be at least 1:1.5. The first etching gas may react with the logic active region to form a barrier layer.

A trench MOSFET includes a substrate, a gate structure, source regions, oxide spacers, a nitride cladding layer, an inner dielectric layer, a source contact, and a gate contact. The gate structure is disposed in a trench of the substrate and has a protruding top exposed from a surface of the substrate and having exposed sidewalls. The source regions are formed in the surface of the substrate on both sides of the gate structure. The oxide spacers are disposed on the exposed sidewalls of the protruding top. The nitride cladding layer conformally covers the oxide spacer and the surface of the substrate. The inner dielectric layer is deposited on the nitride cladding layer. The source contact window passes through the inner dielectric layer and the nitride cladding layer. The gate contact passes through the inner dielectric layer and the nitride cladding layer.