An electronic device is provided. The electronic device includes a substrate, a plurality of first pads, a plurality of second pads, a first data line and a touch signal line. The substrate has a first bonding area and a second bonding area. The first pads are disposed in the first bonding area and arranged along a first direction. The second pads are disposed in the second bonding area and arranged along a second direction. There is an included angle between the first direction and the second direction. The first data line is disposed on the substrate and electrically connected to at least one of the first pads or the second pads. The touch signal line is disposed on the substrate and electrically connected to at least another one of the first pads or the second pads. The first data line at least partially overlaps the touch signal line.

There is provided a memory device including a first chip including a first normal region, the first region including a plurality of first normal connectors on a first surface and configured to be provided with signals used during an operation of memory cells, and a first test region including a plurality of first connectors on the first surface and electrically connected to each other, and a second chip. The second chip includes a second normal region including a plurality of second normal connectors, and configured to provide signals used during the operation of the memory cells to the first normal connectors, and a second test region including a plurality of first and second test connectors on the second surface so as not to overlap the plurality of first connectors in the first direction, and configured to not be provided with signals used during the operation of the memory cells.

A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A narrow border reflective display device includes an driving circuit substrate, a TFT substrate, a front plane laminate, multiple conductive wires, a cover, and a glue. The TFT substrate is located on the driving circuit substrate. The TFT substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the driving circuit substrate and the TFT substrate. The cover is located on the front plane laminate. The glue surrounds the driving circuit substrate, the TFT substrate, the front plane laminate, the front plane laminate, and the conductive wires.

A display panel comprising a display substrate having a display area and a pad area disposed around the display area. A connection wire is disposed on the pad area of the display substrate. A signal wire is disposed on the connection wire. A supporter is disposed between the display substrate and the connection wire. The connection wire directly contacts the supporter.

A backplane and a glass-based circuit board. The backplane includes: a base substrate and a plurality of light-emitting units, arranged in an array on the base substrate. Each of the light-emitting units includes at least one light-emitting sub-unit; the light-emitting sub-unit includes a connection line and a plurality of light-emitting diode chips connected with the connection line, and the light-emitting diode chips are located on a side of the connection line away from the base substrate. The connection line includes a first connection portion, a second connection portion and a third connection portion; in each of the light-emitting sub-units, the third connection portion includes a plurality of connection sub-portions, each of the connection sub-portions includes at least one electrical contact point; the electrical contact points at adjacent ends of adjacent connection sub-portions constitute an electrical contact point pair.

A semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.

Provided is a semiconductor package including a package substrate having a first upper connection pad and a second upper connection pad provided on a top surface of the package substrate, a semiconductor chip disposed on the package substrate, a second semiconductor chip provided on the first semiconductor chip, a plurality of first chip pads and a plurality of second chip pads provided on top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, a plurality of first conductive patterns, a plurality of second conductive patterns, and a cross conductive pattern of which both ends are connected to the first conductive pattern, wherein the cross conductive pattern is provided on a top surface of the first semiconductor chip and the second conductive pattern, and the cross conductive pattern crosses the second cross conductive pattern.

A semiconductor chip may include: a semiconductor substrate; a through silicon via that vertically penetrates the semiconductor substrate; an integrated device layer on a first surface of the semiconductor substrate and including integrated devices; a multi-wiring layer on the integrated device layer and including layers of wires; an upper metal layer on the multi-wiring layer and connected to the wires; and a lower metal layer on a second surface of the semiconductor substrate. The semiconductor substrate may include a lower bump area on the second surface of the semiconductor substrate, the lower bump area including bump pads thereon, and the lower metal layer may be on a periphery of the lower bump area.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.