Described herein is a technique capable of improving the controllability of a thickness of a film formed on a large surface area substrate having a surface area greater than a surface area of a bare substrate and improving the thickness uniformity between films formed on a plurality of large surface area substrates accommodated in a substrate loading region by reducing the influence of the surface area of the large surface area substrate and the number of the large surface area substrates due to a loading effect even when the plurality of large surface area substrates are batch-processed using a batch type processing furnace.

A defect detection method includes: acquiring a photoluminescence detection result of a wafer to be detected; generating a defect heat map corresponding to said wafer according to the photoluminescence detection result and a preset heat map model, the preset heat map model being constructed on the basis of a photoluminescence detection result sample after electroluminescent defect marking; and determining a defect detection result of said wafer according to the defect heat map.

A substrate processing apparatus includes a chamber having a first port and a second port, a stage disposed inside the chamber and configured to support a substrate, a first light emitting system configured to radiate a first incident light through the first port onto the substrate when disposed inside the chamber, a second light emitting system configured to radiate a second incident light through the second port onto an inner surface of a wall of the chamber, and a spectrometer configured to receive a substrate-reflected light reflected from the substrate and a wall-reflected light reflected from the inner surface of the wall of the chamber.

A stealth dicing process for singulating semiconductor dies from a wafer substrate and associated systems and methods are disclosed herein. In some embodiments, the process includes forming a first cleavage line in a wafer that extends generally in a first direction and defines a first surface corresponding to a sidewall of a semiconductor die. The process can also include forming a second cleavage line in the wafer that extends generally in a second direction perpendicular and defines a second surface oriented generally perpendicular to the first surface. Further, the second surface can correspond to at least a portion of a top surface or at least a portion of a bottom surface of the semiconductor die. In some embodiments, the process forms the second cleavage line for a first semiconductor die at a different depth from the second cleavage line for a second semiconductor die.

A method for measuring a thickness of a substrate for a workpiece including the substrate having a first side and a second side disposed in a direction opposite to the first side may be performed by a computing device and may include receiving, from a first measurement device, first side profile information including total surface position information of the first side, receiving, from a second measurement device, a plurality of pieces of substrate sample thickness information indicating sample thicknesses of the substrate measured at a plurality of sampling points on the first side, and generating, based on the first side profile information and the plurality of pieces of substrate sample thickness information, a substrate thickness map including total thickness information of the substrate.

Semiconductor devices with die overthinning detection circuitry (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a semiconductor die includes a substrate, a triple well structure positioned at least partially within the substrate, and circuitry. The triple well structure can form a depletion region within the substrate, and the circuitry can be configured to capture a measurement of an amount of leakage current from the depletion region while a reverse bias is applied across the triple well structure. In some embodiments, the reverse bias can be applied across the triple well structure using part of a metallization die border of the semiconductor die. In these and other embodiments, measurement of the amount of leakage current can be used to detect that the semiconductor die is defective (e.g., overthinned, overpolished).

A thermal control system comprising an integrated heater and cold plate is disclosed. The integrated heater and cold plate comprises a heat transfer geometry for transferring heat from the heater to the cold plate. The heat transfer geometry may comprise a plurality of fins configurable for changing the heat transfer rate between the heater and the cold plate. For example, the number of fins, spacing between fins, size of the base of the cold plate, fluid flow through the fins, etc. may be configured to increase or decrease the heat transfer rate. In some examples, the heat transfer geometry may be deposited directly on or permanently attached to the base of the cold plate or heater. In some examples, the heater may directly contact the heat transfer geometry. The thermal control system may not include air or a thermal interface material (TIM) between the heater and the heat transfer geometry.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

A method of polishing a layer on the substrate at a polishing station includes the actions of monitoring the layer during polishing at the polishing station with an in-situ monitoring system to generate a plurality of measured signals for a plurality of different locations on the layer; generating, for each location of the plurality of different locations, an estimated measure of thickness of the location, the generating including processing the plurality of measured signals through a neural network; and at least one of detecting a polishing endpoint or modifying a polishing parameter based on each estimated measure of thickness.

A method for processing substrates includes subjecting each respective first substrate of a first plurality of substrates to a process that modifies a thickness of an outer layer of the respective first substrate, generating a plurality of groups of process parameter values; generating a plurality of removal profiles, training an artificial neural network by backpropagation using the plurality of groups of process parameter and plurality of removal profiles as training data where the artificial neural network has a plurality of input nodes to receive respective removal values from the removal profile and a plurality of output nodes to output control parameter values, for each respective second substrate of a second plurality of substrates determining a target removal profile, determining respective control parameter values to apply by applying the target removal profile to the input nodes, and subjecting each respective second substrate to the process using the respective control parameter values.