The present document relates to a method of monitoring an overlay or alignment between a first and second layer of a semiconductor using a scanning probe microscopy system. The method comprises scanning the substrate surface using a probe tip for obtaining a measurement of a topography of the first and second layer in at least one scanning direction. At least one pattern template is generated which is matched with the topography of the first layer for determining a first candidate pattern. The first candidate pattern is matched with the measured second topography for obtaining a second candidate pattern to represent the measured topography of the second layer. Feature characteristics of device features are determined from both the first and second candidate pattern, and these are used to calculate one or more overlay parameters or alignment parameters.

An example method includes obtaining data indicative of a workpiece processing parameter. In some implementations, the example method includes determining a grinding depth for a semiconductor workpiece based at least in part on the data indicative of the workpiece processing parameter. In some implementations, the example method includes performing a grinding operation to remove material from the semiconductor workpiece to reduce a thickness of the semiconductor workpiece by the grinding depth.

A system includes a processing unit communicatively coupled to a detector array of an optical wafer characterization system. The processing unit is configured to perform one or more steps of a method or process including the steps of acquiring one or more target images of a target location on a wafer from the detector array, applying a de-noising filter to at least the one or more target images, determining one or more difference images from one or more reference images and the one or more target images, and up-sampling the one or more difference images to generate one or more up-sampled images. One or more wafer defects are detectable in the one or more difference images or the up-sampled images.

A heat treatment apparatus is a heat treatment apparatus managing a dummy wafer. The heat treatment apparatus includes: a heat treatment part performing a heat treatment on the dummy wafer; a damage detection part detecting a damage of the dummy wafer; and a controller determining whether or not the dummy wafer can be used based on damage information detected by the damage detection part.

Methods and systems for processing a bevel edge of a wafer in a bevel plasma chamber. The method includes receiving a pulsed mode setting for a RF generator of the bevel plasma chamber. The method includes identifying a duty cycle for the pulsed mode, the duty cycle defining an ON time and an OFF time during each cycle of power delivered by the generator. The method includes calculating or accessing a compensation factor to an input RF power setting of the generator. The compensation factor is configured to add an incremental amount of power to the input power setting to account for a loss in power attributed to the duty cycle to be run in the pulsed mode. The method is configured to run the generator in the pulse mode with the duty cycle and the pulsing frequency. The generator is configured to generate the input power in pulsing mode that includes incremental amount of power to achieve an effective power in the bevel plasma chamber to achieve a target bevel processing throughput, while reducing charge build-up that causes arcing damage.

There is an inspection system including multiple inspection units configured to inspect substrates, wherein each of the inspection units includes: a tester configured to inspect a substrate; a moving part configured to hold and move the substrate relative to the tester; and a frame structure configured to accommodate the tester and the moving part, wherein the frame structure of one inspection unit includes: a first frame to be connected to a frame structure of another inspection unit; and a second frame that accommodates at least the moving part and is configured to move relative to the first frame to extract the moving part from the first frame.

In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.

A detection method for a semiconductor structure, which includes providing a test element group. The test element group includes a plurality of isolation structures and a first word line and a second word line disposed in each of the isolation structures. The first word line and the second word line are on opposite sides of each of the isolation structures. The detection method further includes performing a first etching process on the test element group to remove the upper portion of the isolation structures and expose the top surface of active regions of the test element group. The detection method further includes performing a second etching process on the test element group, and the second etching process is a wet etching process. The detection method further includes performing a defect test on the test element group to determine whether the test element group contains a word line defect.

Systems and methods of processing semiconductor wafers using nanotopography analysis of a front-end processed (e.g., ground) wafer surface. The systems and methods execute a wafer analysis model that filters out roughness defects from the front-end processed wafer surface to enable the nanotopography analysis. In one example, a method of processing semiconductor wafers includes obtaining image data of a surface of a pre-polished wafer; processing the image data by: generating linear profiles of the surface, applying a regression analysis to smooth each linear profile, and recombining the smoothed linear profiles to obtain processed image data; determining a nanotopography of the surface of the pre-polished wafer from the processed image data; and based on the determined nanotopography of the surface, either sorting the pre-polished wafer for polishing or adjusting a front end process performed on the pre-polished wafer.

A method of manufacturing a semiconductor element includes preparing integrated circuit chips, obtaining warpage information of each of the integrated circuit chips, deforming at least a portion of a chip stress control pattern of each of the integrated circuit chips according to the warpage information of each of the integrated circuit chips, laminating the integrated circuit chips on a carrier substrate with adhesive layers interposed therebetween, curing the adhesive layers, and removing chip scribe lane areas from the integrated circuit chips.