Monitoring operations of a polishing system includes obtaining a time-based sequence of reference images of a component of the polishing system performing operations during a test operation of the polishing system, receiving from a camera a time-based sequence of monitoring images of an equivalent component of an equivalent polishing system performing operations during polishing of a substrate, determining a difference value for the time-based sequence of monitoring images by comparing the time-based sequence of reference images to the time-based sequence of monitoring image using an image processing algorithm, determining whether the difference value exceeds a threshold, and in response to determining the difference value exceeds the threshold, indicating an excursion.

A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.

A control device configured to control a supply condition of a gas which is supplied between two substrates that are to be bonded to each other by a substrate bonding device, is configured to control the supply condition based on a measurement result obtained by a measurement in relation to at least one of the substrate, another substrate bonded before the substrate is bonded, or the substrate bonding device, and the two substrates are bonded to each other by a contact region expanding after the contact region is formed in a center.

Embodiments herein are directed to localized wafer thickness correction. In some embodiments, a method may include providing a substrate including an upper surface having a raised portion extending above a plane defined by the upper surface, and a non-raised portion adjacent the raised portion. The method may further include performing a metrology scan of the upper surface to determine a first dimension of the raised portion and a second dimension of the non-raised portion, and depositing a hardmask over the upper surface, including over the raised portion and the non-raised portion. The method may further include directing ions to the hardmask, wherein a first dose of the ions over the raised portion is greater than a second dose of the ions over the non-raised portion, and performing a first etch to the hardmask to remove the hardmask over the raised portion, wherein the hardmask remains over the non-raised portion.

An electronic product includes a number of die and an interposer. The die are coupled to the interposer. Each respective die includes an edge integrity detection structure extending along at least part of an edge of the respective die. The interposer includes at least one pad coupled to at least one edge integrity detection structure of the die.

A method of increasing a volume and a height of a solder bump present on a contact pad of a substrate is provided, including the steps: a) placing a solder ball having a predetermined volume in a capillary which is placed over the solder bump, b) liquefying the solder ball by applying laser energy from the laser source to the solder ball through the capillary, c) ejecting the liquefied solder ball from the capillary onto the solder bump by applying pressurized gas to the liquefied solder ball through the capillary, and d) melting the solder bump by transferring thermal and kinetic energy to the solder bump from the ejected liquefied solder ball and merging the liquefied solder ball with the melted solder bump.

A bonding strength evaluation method may include preparing bonded wafers, separating the bonded wafers by applying a force to one surface of the bonded wafers in a direction perpendicular to the one surface of the bonded wafers, measuring at least one of the force applied to the one surface of the bonded wafers, a time when the force is applied, a separation distance between the bonded wafers, a length of an area where the bonded wafers are separated, and determining a bonding strength based on at least one of the force, the time during which the force is applied, the separation distance between the bonded wafers, and the length of the area where the bonded wafers are separated.

Various aspects relate to electronic memory devices and mechanisms for communicating with electronic memory devices. A plurality of stacked semiconductor wafers forms a wafer stack. A logic base die is configured to support the plurality of stacked semiconductor wafers. At least one through silicon via is formed through the plurality of stacked semiconductor wafers, wherein the at least one through silicon via is configured to form an inductive coil that is configured to provide a communication interface to the plurality of stacked semiconductor wafers.

A method of inspecting a wafer dicing process entails performing a scanning process on a grooved wafer with a light beam used by an optical scanning device. The method includes using a film layer of the grooved wafer as an incident surface for the scanning process; performing the scanning process on the grooved wafer in a Y-axis direction to obtain XZ section structure images corresponding in position to consecutive different Y-axis positions on the grooved wafer; analyzing the XZ section structure images at the consecutive different positions and defining positions corresponding in position to grooves, the film layer, a silicon layer and a metal layer; and analyzing a depth of each of the grooves to determine whether the grooved wafer is grooved successfully or grooved unsuccessfully. Therefore, the method is applicable to wafer processing procedures and addresses the lack of inspection methods in the wafer dicing process.

The invention provides an overlay mark, which comprises four sub-overlay marks, which together form an overlay mark, wherein each sub-overlay mark comprises a substrate and defines an inner region and an outer region, a plurality of first mandrel structures located in the inner region and a plurality of second mandrel structures located in the outer region, wherein the first mandrel structures are arranged in parallel with each other, and the second mandrel structures are also arranged in parallel with each other, and a plurality of strip-shaped mask layers are located in the inner region, wherein both sides of any first mandrel structure comprise a strip-shaped mask layer respectively. In addition, the invention also provides an overlay method of the semiconductor structure using the overlay mark.