An apparatus is provided. The apparatus includes a disk configured to rotate during an ion implantation process. The apparatus includes a wafer support assembly coupled to the disk and configured to support one or more semiconductor wafers. The rotation of the disk causes the one or more semiconductor wafers to revolve along a path. The apparatus includes an ion implanter configured to emit an ion beam to a beam position along the path. The apparatus includes a vibration calibration device including a calibration base coupled to the disk and a first calibration unit coupled to the calibration base. The vibration calibration device is configured to move the first calibration unit from a first position to a second position to reduce a vibration associated with the apparatus.

A control device for controlling a state quantity in a substrate processing apparatus performing processing on a substrate, the control device includes: a feedback controller configured to apply a control signal to a control target, based on a deviation between a target value of the state quantity and a detected value from a detector; and a correction value calculator configured to acquire a deviation e.sub.j between the target value and the detected value in j-th substrate processing (where j is an integer of 1 or greater) and calculate a correction value to be added to the control signal from the feedback controller during (j+1)-th substrate processing, so that a deviation e.sub.j+1 between the target value and the detected value in the (j+1)-th substrate processing becomes smaller than the deviation e.sub.j.

A method includes forming a plurality of dies on one or more first substrates. The method further includes stacking multiple dies of the plurality of dies on a second substrate to form a die stack. The method further includes forming a through-via in the die stack. The through-via electrically couples each of the multiple dies of the die stack.

Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.

An apparatus for chemical mechanical polishing of a wafer includes a process chamber and a rotatable platen disposed inside the process chamber. A polishing pad is disposed on the platen and a wafer carrier is disposed on the platen. A slurry supply port is configured to supply slurry on the platen. A process controller is configured to control operation of the apparatus. A set of microphones is disposed inside the process chamber. The set of microphones is arranged to detect sound in the process chamber during operation of the apparatus and transmit an electrical signal corresponding to the detected sound. A signal processor is configured to receive the electrical signal from the set of microphones, process the electrical signal to enable detection of an event during operation of the apparatus, and in response to detecting the event, transmit a feedback signal to the process controller. The process controller is further configured to receive the feedback signal and initiate an action based on the received feedback signal.

A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

A system includes a vacuum chamber having a wafer chuck therein and side windows slanted relative to the wafer chuck. A wafer stage is positioned below the wafer chuck and configured to rotate the wafer chuck and move the wafer chuck vertically. Illumination optics, including an illumination corrector lens, are configured to receive light and direct the light through an illumination vacuum window of the side windows to an optical spot on the wafer. Collection optics, including a collection corrector lens, are configured to receive the light from the optical spot through a collection vacuum window of the side windows and direct the light to a detector. A transfer module is configured to move the illumination optics and the collection optics parallel to the illumination vacuum window and the collection vacuum window respectively. The illumination corrector lens and the collection corrector lens are configured to reduce chromatic aberration.

A method of creating a correlation relational formula for determining a polishing condition, the method including polishing semiconductor wafers under a plurality of polishing conditions including a plurality of polishing parameters, and acquiring, by actual measurement, in-plane polishing amount distribution information on the semiconductor wafers in polishing under the plurality of polishing conditions; polishing semiconductor wafers under a plurality of polishing conditions including a plurality of polishing parameters, and acquiring, by actual measurement, in-plane temperature distribution information during semiconductor wafer polishing in polishing under the plurality of polishing conditions, or creating in-plane temperature distribution information during semiconductor wafer polishing under polishing conditions including a plurality of polishing parameters by heat transfer analysis, and correlating relational formulas between a semiconductor wafer in-plane temperature distribution parameter and a plurality of polishing parameters.

A method of forming a semiconductor structure includes forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate in sequence; forming a second dielectric layer on a portion of the metal layer; forming a BPSG layer on the second dielectric layer; etching the metal layer and the semiconductor layer; forming a first spacer layer on sidewalls of the semiconductor layer, the metal layer, and the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.

Load lock assemblies, semiconductor processing systems including such load lock assemblies, and associated methods for monitoring process drift within a process module of a semiconductor processing system are disclosed. The load lock assemblies disclosed include an indexer mechanism and position sensor in communication with a controller in a feedback loop configuration to enable the generation of a control parameter based on the weight or the weight change of a substrate within the load lock assembly. The control parameter is used to signal when a process drift is detected to enable corrective measures to be performed.