A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*10.sup.10 cm.sup.2 eV.sup.1 to 1.2*10.sup.10 cm.sup.2 eV.sup.1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

A support substrate for a radiofrequency application comprises: a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm.Math.cm and strictly less than 500 ohm.Math.cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm.Math.cm, a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm.Math.cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.

A method for manufacturing a support substrate comprising a charge-trapping layer for a semiconductor-on-insulator or piezoelectric-on-insulator structure for a radio-frequency application, includes: placing a base substrate comprising a layer of native silicon oxide in a deposition chamber; raising the temperature of the deposition chamber to a deposition temperature of the charge-trapping layer; introducing an oxidizing gas into the deposition chamber in order to preserve the layer of native silicon oxide during the temperature rise; venting the oxygen from the deposition chamber at the formation temperature of the charge-trapping layer; and-depositing, in the deposition chamber, the charge-trapping layer of polycrystalline silicon on the layer of native silicon oxide.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.

A stacked substrate of an embodiment is a stacked substrate for separating a semiconductor substrate using thermal expansion by a laser beam, the stacked substrate including the semiconductor substrate, a first insulating layer disposed above the semiconductor substrate, and a polysilicon layer that is disposed in contact with the first insulating layer, a thickness of the polysilicon layer being larger than a thickness of the first insulating layer in a direction perpendicular to a surface of the semiconductor substrate, and the polysilicon layer being doped with phosphorus.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.