There is provided a memory device including a first chip including a first normal region, the first region including a plurality of first normal connectors on a first surface and configured to be provided with signals used during an operation of memory cells, and a first test region including a plurality of first connectors on the first surface and electrically connected to each other, and a second chip. The second chip includes a second normal region including a plurality of second normal connectors, and configured to provide signals used during the operation of the memory cells to the first normal connectors, and a second test region including a plurality of first and second test connectors on the second surface so as not to overlap the plurality of first connectors in the first direction, and configured to not be provided with signals used during the operation of the memory cells.

A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX1 and PX2, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY1 and PY2, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.

[00001]$\begin{array}{cc}\mathrm{PX}1>\mathrm{PY}1& \left(1\right)\end{array}$$\begin{array}{cc}\mathrm{PY}2>\mathrm{PX}2& \left(2\right)\end{array}$

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.

Provided is a semiconductor package including a three-dimensional (3D) stacked structure in which an upper second semiconductor chip is stacked on a lower first semiconductor chip. In the semiconductor package, a power distribution network for the first semiconductor chip and a power distribution network for the second semiconductor chip are implemented through circuits of the first semiconductor chip and separated from the first semiconductor chip.

A possible benefit of the present disclosure is to further improve a heat dissipation property of an electronic component. A high-frequency module includes a mounting substrate, a filter (for example, a transmission filter), a resin layer, a shielding layer, and a metal member. The resin layer covers at least a portion of an outer peripheral surface (for example, an outer peripheral surface) of the filter. The shielding layer covers at least a portion of the resin layer. The metal member is disposed at a first principal surface of the mounting substrate. The metal member is connected to a surface of the filter on the opposite side from the mounting substrate, the shielding layer, and the first principal surface of the mounting substrate.

Systems and apparatus are provided for a hybrid wire size diameter under one single die. For example, an apparatus can include a memory cell die, a plurality of signal pads under the memory cell die and a plurality of power pads under the memory cell die. Each bonding wire coupled to a respective one of the plurality of signal pads has a first wire size diameter and each bonding wire coupled to a respective one of the plurality of power pads has a second wire size diameter larger than the first wire size diameter.

A semiconductor package includes a substrate including a first surface and a second surface, and a first substrate pad on the second surface, a first semiconductor chip on the second surface and including a third surface and a fourth surface, a first hotspot within the first semiconductor chip, and a first chip pad on the fourth surface, a first dummy pad on the fourth surface, a first layer connecting the first hotspot and the first dummy pad, a first pillar on the first dummy pad, a mold film on the substrate and including a fifth surface and a sixth surface, a thermal interface material layer on the mold film, and a heat slug on the thermal interface material layer; the mold film includes a first recess recessed inwardly from the sixth surface of the mold film, and at least part of the thermal interface material layer is in the recess.

An IC structure includes a memory stack including a plurality of semiconductor die. The semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface, four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within an upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die. One the semiconductor die includes at least one thermal edge portion exposed from the second sidewall.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.