An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

A semiconductor device includes a semiconductor layer, an element isolation portion that is formed at the semiconductor layer and that defines an element region in the semiconductor layer, and a first contact that is formed in a linear shape along the element isolation portion in a plan view and that is electrically connected to the element isolation portion. The semiconductor device further includes a semiconductor substrate supporting the semiconductor layer and a buried layer formed so as to be contiguous to the semiconductor layer, and the element isolation portion may reach the semiconductor substrate through the buried layer from a front surface of the semiconductor layer.

A method for forming an SOI substrate includes following operations. A first semiconductor layer, a second semiconductor layer and a third semiconductor layer are formed over a first substrate. A plurality of trenches and a plurality of recesses are formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer. The plurality of trenches extend along a first direction, and the plurality of recesses extend along a second direction different from the first direction. The plurality of trenches and the plurality of recesses are sealed to form a plurality of voids. A device layer is formed over the first substrate. The devices layer is bonded to an insulator layer over a second substrate. The third semiconductor layer, the device layer the insulator layer and the second substrate are separated from the first semiconductor layer and the first substrate. The device layer is exposed.

A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

A method of fabricating a semiconductor device includes forming a first shallow trench isolation structure in a first region of a substrate and second shallow trench isolation structures in a second region of the substrate. The method also includes forming a mask layer over the substrate, the first shallow trench isolation structure, and the second shallow trench isolation structures. The method further includes etching the mask layer and second shallow trench isolation structures in the second region sequentially to form a semiconductor protrusion between the second shallow trench isolation structures.

The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture and operation. The structure includes: a semiconductor on insulator substrate; an insulator layer under the semiconductor on the insulator substrate; a handle substrate under insulator layer; a first well of a first dopant type in the handle substrate; a second well of a second dopant type in the handle substrate, adjacent to the first well; and a back-gate diode at a juncture of the first well and the second well.

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

A semiconductor device includes a semiconductor substrate, a base region, an emitter region, a collector region, and an element isolation insulating film. The semiconductor substrate has a main surface. The base region has a first conductivity type and is disposed in a surface layer of the semiconductor substrate that is close to the main surface. The emitter region has a second conductivity type and is disposed in a surface layer of the base region. The collector region has the second conductivity type and is disposed at a portion in the surface layer of the semiconductor substrate apart from the emitter region. The element isolation insulating film is disposed on the main surface, and has a thermal oxide film being in contact with a junction interface between the base region and the emitter region.

A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A well is in the base layer, a doped region is above and coupled with the well, and the doped region is in the insulator layer. A drift region is above and coupled with the doped region, and the drift region is at least partially in the semiconductor layer. A gate stack is partially over the semiconductor layer and partially over drift region.