Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A semiconductor device includes a first structure including a first insulating layer and a first conductive wiring arranged on the first insulating layer, a second-1 insulating layer arranged above the first structure in a first direction, a via hole penetrating the second-1 insulating layer in the first direction, a barrier layer arranged at a lower side of the via hole, and a via plug electrically connected to the first conductive wiring and arranged to fill a remaining space in an internal space of the via hole, excluding the barrier layer.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

A semiconductor die including a semiconductor substrate, an interconnect structure, a capacitor structure, a redistribution layer and a bonding structure is provided. The interconnect structure is disposed on the semiconductor substrate. The capacitor structure is disposed on the interconnect structure. The redistribution layer is disposed on and electrically connected to the interconnect structure. The bonding conductor is electrically and physically in contact with the capacitor structure at a sidewall of the bonding conductor, wherein the redistribution layer is located at a lower level than the bonding conductor.

An integrated circuit (IC) may include a pillar bar disposed in a bar area over a row of transistors to conduct a current through the transistors and to conduct heat away from the transistors. The pillar bar includes a top metal layer, a bottom metal layer coupled to a terminal of each of the transistors in the row, and at least one intermediate layer between the top metal layer and the bottom metal layer. When heated by the transistors, the metal in the pillar bar expands at a different rate than the IC substrate, causing heat-related stress that may damage the IC. In a pillar bar disclosed herein, one of the intermediate layers includes separate metal regions separated by a non-metal material in the bar area. The pillar bar includes a central metal region and separate metal regions between the central metal region and the ends of the pillar bar.

Split processing of integrated circuit layers with high accuracy bonding is described. In an example, an integrated circuit structure includes a front-end-of-line (FEOL) stack having an uppermost surface including first conductive features and first dielectric features. A back-end-of-line (BEOL) stack is above the FEOL stack. The BEOL stack has a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the uppermost surface of the FEOL stack, respectively. The second conductive features are laterally offset from the corresponding first conductive features.

A semiconductor device includes a substrate having an active region; a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; a via contact disposed in the first insulating layer and electrically connected to the active region; an interconnection structure disposed in the second insulating layer and electrically connected to the via contact; and an etch stop layer disposed between the first insulating layer and the second insulating layer. The etch stop layer includes an upper layer region, a lower layer region and an intermediate film between the upper layer region and the lower layer region. Each of the upper layer region and the lower layer region includes a compound that includes a first element, and an intermediate film includes a second element intermixed with the first element.

A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.