SPLIT PROCESSING OF INTEGRATED CIRCUIT LAYERS WITH HIGH ACCURACY BONDING

Abstract

Split processing of integrated circuit layers with high accuracy bonding is described. In an example, an integrated circuit structure includes a front-end-of-line (FEOL) stack having an uppermost surface including first conductive features and first dielectric features. A back-end-of-line (BEOL) stack is above the FEOL stack. The BEOL stack has a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the uppermost surface of the FEOL stack, respectively. The second conductive features are laterally offset from the corresponding first conductive features.

Claims

1. An integrated circuit structure, comprising: a front-end-of-line (FEOL) stack having an uppermost surface including first conductive features and first dielectric features; and a back-end-of-line (BEOL) stack above the FEOL stack, the BEOL stack having a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the uppermost surface of the FEOL stack, respectively, wherein the second conductive features are laterally offset from the corresponding first conductive features.

2. The integrated circuit structure of claim 1, wherein the first and second conductive features comprise copper, and the first and second dielectric features comprise silicon and oxygen.

3. The integrated circuit structure of claim 1, wherein the FEOL stack comprises gate-all-around-based devices.

4. The integrated circuit structure of claim 1, wherein the FEOL stack comprises fin-based devices.

5. The integrated circuit structure of claim 1, further comprising: a backside stack having an uppermost surface in contact with a bottommost surface of the FEOL stack.

6. An integrated circuit structure, comprising: a front-end-of-line (FEOL) stack having a bottommost surface including first conductive features and first dielectric features; and a backside stack below the FEOL stack, the backside stack having an uppermost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the bottommost surface of the FEOL stack, respectively, wherein the second conductive features are laterally offset from the corresponding first conductive features.

7. The integrated circuit structure of claim 6, wherein the first and second conductive features comprise copper, and the first and second dielectric features comprise silicon and oxygen.

8. The integrated circuit structure of claim 6, wherein the FEOL stack comprises gate-all-around-based devices.

9. The integrated circuit structure of claim 6, wherein the FEOL stack comprises fin-based devices.

10. The integrated circuit structure of claim 6, further comprising: a back-end-of-line (BEOL) stack having a bottommost surface in contact with an uppermost surface of the FEOL stack.

11. A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a front-end-of-line (FEOL) stack having a surface including first conductive features and first dielectric features; and a back-end-of-line (BEOL) stack above the FEOL stack, the BEOL stack having a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the surface of the FEOL stack, respectively, wherein the second conductive features are laterally offset from the corresponding first conductive features, or a backside stack below the FEOL stack, the backside stack having an uppermost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the surface of the FEOL stack, respectively, wherein the second conductive features are laterally offset from the corresponding first conductive features.

12. The computing device of claim 11, comprising the BEOL stack above the FEOL stack.

13. The computing device of claim 11, comprising the backside stack below the FEOL stack.

14. The computing device of claim 11, further comprising: a memory coupled to the board.

15. The computing device of claim 11, further comprising: a communication chip coupled to the board.

16. The computing device of claim 11, further comprising: a battery coupled to the board.

17. The computing device of claim 11, further comprising: a camera coupled to the board.

18. The computing device of claim 11, further comprising: a display coupled to the board.

19. The computing device of claim 11, wherein the component is a packaged integrated circuit die.

20. The computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIGS. 1A-1B illustrate cross-sectional views representing various operations in a method in which two independent wafers are generated for front end and backend sections, in accordance with an embodiment of the present disclosure.

[0005] FIG. 1C illustrates a cross-sectional view of a structure composed of two bonded portions and, in accordance with an embodiment of the present disclosure.

[0006] FIGS. 1D-1E illustrate cross-sectional views representing various operations in a method in which three independent wafers are generated for front end and backside power layers, in accordance with an embodiment of the present disclosure.

[0007] FIG. 2 illustrates cross-sectional views of an interconnect stack having front side power delivery and of an interconnect stack having backside power delivery, in accordance with an embodiment of the present disclosure.

[0008] FIG. 3 illustrates a cross-sectional view of an integrated circuit structure having a nanowire layer and backside power delivery, in accordance with an embodiment of the present disclosure.

[0009] FIGS. 4A-4J illustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure.

[0010] FIG. 5 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure.

[0011] FIG. 6 is a schematic of a pitch quartering approach used to fabricate trenches for interconnect structures, in accordance with an embodiment of the present disclosure.

[0012] FIG. 7A illustrates a cross-sectional view of a metallization layer fabricated using pitch quartering scheme, in accordance with an embodiment of the present disclosure.

[0013] FIG. 7B illustrates a cross-sectional view of a metallization layer fabricated using pitch halving scheme above a metallization layer fabricated using pitch quartering scheme, in accordance with an embodiment of the present disclosure.

[0014] FIG. 8A illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition above a metallization layer with a differing metal line composition, in accordance with an embodiment of the present disclosure.

[0015] FIG. 8B illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition coupled to a metallization layer with a differing metal line composition, in accordance with an embodiment of the present disclosure.

[0016] FIGS. 9A-9C illustrate cross-section views of individual interconnect lines having various liner and conductive capping structural arrangements, in accordance with an embodiment of the present disclosure.

[0017] FIG. 10 illustrates a cross-sectional view of an integrated circuit structure having four metallization layers with a metal line composition and pitch above two metallization layers with a differing metal line composition and smaller pitch, in accordance with an embodiment of the present disclosure.

[0018] FIG. 11 illustrates a cross-sectional view of a stack of metallization layers including a conductive line plug at a lower metal line location, in accordance with an embodiment of the present disclosure.

[0019] FIG. 12 illustrates a computing device in accordance with one implementation of the disclosure.

[0020] FIG. 13 illustrates an interposer that includes one or more embodiments of the disclosure.

[0021] FIG. 14 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0022] FIG. 15 illustrates a cross-sectional view of a flip-chip mounted die, in accordance with an embodiment of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

[0023] Advanced integrated circuit structure fabrication is described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0024] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word exemplary means serving as an example, instance, or illustration. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

[0025] This specification includes references to one embodiment or an embodiment. The appearances of the phrases in one embodiment or in an embodiment do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0026] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure (including the appended claims):

[0027] Comprising. This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or operations.

[0028] Configured To. Various units or components may be described or claimed as configured to perform a task or tasks. In such contexts, configured to is used to connote structure by indicating that the units or components include structure that performs those task or tasks during operation. As such, the unit or component can be said to be configured to perform the task even when the specified unit or component is not currently operational (e.g., is not on or active). Reciting that a unit or circuit or component is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. 112, sixth paragraph, for that unit or component.

[0029] First, Second, etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0030] CoupledThe following description refers to elements or nodes or features being coupled together. As used herein, unless expressly stated otherwise, coupled means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

[0031] In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as upper, lower, above, and below refer to directions in the drawings to which reference is made. Terms such as front, back, rear, side, outboard, and inboard describe the orientation or location or both of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0032] InhibitAs used herein, inhibit is used to describe a reducing or minimizing effect. When a component or feature is described as inhibiting an action, motion, or condition it may completely prevent the result or outcome or future state completely. Additionally, inhibit can also refer to a reduction or lessening of the outcome, performance, or effect which might otherwise occur. Accordingly, when a component, element, or feature is referred to as inhibiting a result or state, it need not completely prevent or eliminate the result or state.

[0033] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0034] Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0035] Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

[0036] It is to be appreciated that FEOL is a technology driver for a given process. In other embodiment, FEOL considerations are driven by BEOL 10 nanometer or sub-10 nanometer processing requirements. For example, material selection and layouts for FEOL layers and devices may need to accommodate BEOL processing. In one such embodiment, material selection and gate stack architectures are selected to accommodate high density metallization of the BEOL layers, e.g., to reduce fringe capacitance in transistor structures formed in the FEOL layers but coupled together by high density metallization of the BEOL layers.

[0037] Back-end-of-line (BEOL) layers of integrated circuits commonly include electrically conductive microelectronic structures, which are known in the art as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias may be formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

[0038] Sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up.

[0039] Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Shrink technologies exist to shrink the critical dimensions of the via openings. However, the shrink amount tends to be limited by the minimum via pitch, as well as by the ability of the shrink process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) or critical dimension uniformity (CDU), or both. Yet another such challenge is that the LWR or CDU, or both, characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease in order to maintain the same overall fraction of the critical dimension budget.

[0040] The above factors are also relevant for considering placement and scaling of non-conductive spaces or interruptions between metal lines (referred to as plugs, dielectric plugs or metal line ends among the metal lines of back-end-of-line (BEOL) metal interconnect structures. Thus, improvements are needed in the area of backend metallization manufacturing technologies for fabricating metal lines, metal vias, and dielectric plugs.

[0041] One or more embodiments described herein are directed to split processing of fab layers with high accuracy bonding. One or more embodiments described herein are directed to integrated circuit structures formed using split processing and bonding and including gate-all-around-based devices or circuits. It is to be appreciated that, unless indicated otherwise, reference to nanowires can indicate nanowires or nanoribbons or nanosheets. One or more embodiments described herein are directed to integrated circuit structures formed using split processing and bonding and including fin-based devices or circuits. One or more embodiments described herein are directed to integrated circuit structures formed using split processing and bonding and including planar-based devices or circuits, where a device is formed on a planar semiconductor surface versus a non-planar surface.

[0042] To provide context, highly complicated semiconductor manufacturing takes several months to process from FEOL to BEOL. This long processing time can impact the throughput and yield learning. As FEOL/BEOL are typically processed in the same fab, the fab spaces/capacity can be limited to process the entire flow in a single fab.

[0043] Currently, a key approach is to improve cycle time of each operation to improve throughput. Multiple factories are often built to accommodate growing demand of semiconductor processing. Each factory has a replica of FEOL and BEOL in order to support the demand.

[0044] One or more embodiments described herein are directed to the processing of a front end and a backend in separate wafers. In an embodiment, using high accuracy bonding techniques, the wafers with front end and backend layers are bonded together to produce a final configuration. In an embodiment, the bonding process can be performed in wafer to wafer (W2W) or Chip to Wafer (C2W) schemes.

[0045] Advantages for implementing one or more embodiments described herein can include enabling front end (FE) and backend (BE) wafers are processed independently, which can shorten manufacturing lead time significantly and accelerate yield learning. FE/BE wafers can be processed in different fabs, or on a different processing schedule and inventory management, relieving capacity constraints in individual factories. A FE-BE process can be decoupled, so that additional BE processing such as anneal or plasma process, may not be impacting transistor performance. Prior to bonding, optional removable layers can be added to sort each wafer functionally before bonding, in order to enable a known-good-die scheme. In an embodiment, one or more optional removable redistribution layers (RDLs) are included to sort each wafer.

[0046] Detection of the implementation of one or more embodiments described herein can include the observation of a bonding structure between front and backend intersection using cross-section TEM. An alignment mark that may be used for bonding can be detected by xSEM or xTEM. Any misaligned layer at a bonding interface can be an indication of a bonding layer, such as described below in association with FIG. 1C. If a chip to wafer scheme is used, the size of a bottom and top die can be different and an extra inter-layer dielectric (ILD) feature may be present in a scribeline area. Such a feature may be detected with xSEM. After FIB thinning, top-down inspection of a bonding structure may be used to identify embodiments described herein.

[0047] As an exemplary process, FIGS. 1A-1B illustrate cross-sectional views representing various operations in a method in which two independent wafers are generated for front end and backend sections, in accordance with an embodiment of the present disclosure.

[0048] Referring to part (a) of FIG. 1A, a starting structure 100 (which can be referred to as a wafer 2 structure) includes a carrier wafer or substrate 102, such as a silicon wafer or substrate. A dielectric layer 104, such as a silicon oxide or silicon dioxide layer, is on the carrier wafer or substrate 102. A back-end-of-line (BEOL) stack 106 is on the dielectric layer 104. The BEOL stack 106 includes one or more layers of conductive lines 108 and vias 110, which can be referred to as metallization layers, e.g., in a surrounding dielectric layer or stack of dielectric layers.

[0049] Referring to part (b) of FIG. 1A, a carrier wafer or substrate 114, such as a silicon wafer or substrate, and a dielectric layer 112, such as a silicon oxide or silicon dioxide layer, are coupled to the BEOL stack 106.

[0050] Referring to part (c) of FIG. 1A, a starting structure 116 (which can be referred to as a wafer 1 structure) includes a carrier wafer or substrate 118, such as a silicon wafer or substrate. A dielectric layer 120, such as a silicon oxide or silicon dioxide layer, is on the carrier wafer or substrate 118. A front-end-of-line (FEOL) stack 122 is on the dielectric layer 120. The FEOL stack 122 includes one or more layers of devices 124A and 124B, such as complementary metal oxide semiconductor (CMOS) devices, and one or more layers of device contacts 126A and 126B, e.g., in a surrounding dielectric layer or stack of dielectric layers.

[0051] Referring to part (d) of FIG. 1A, an arrangement 130 includes starting structure 116 and a structure 128. Structure 128 represents the structure of part (b) of FIG. 1A having the carrier wafer or substrate 102 and the dielectric layer 104 removed, and the resulting structure inverted to provide BEOL stack 106A as inverted.

[0052] Referring to part (e) of FIG. 1B, the arrangement 130 from part (d) of FIG. 1A is shown as a starting structure.

[0053] Referring to part (f) of FIG. 1B, a unified structure 132 is provided by bonding the starting structure 116 to the structure 128. In one embodiment, the unified structure 132 is achieved using metal-to-metal bonding between the starting structure 116 and the structure 128. In one embodiment, the unified structure 132 is achieved using dielectric-to-dielectric bonding between the starting structure 116 and the structure 128. In one embodiment, the unified structure 132 is achieved using both metal-to-metal bonding and dielectric-to-dielectric bonding between the starting structure 116 and the structure 128. It is to be appreciated that for hybrid bonding, both metal-to-metal bonding and dielectric-to-dielectric bonding are employed.

[0054] Referring to part (g) of FIG. 1B, an integrated circuit structure 138 is formed by removing the carrier wafer or substrate 114 from below the BEOL stack 106A. Conductive bumps 136 can be formed on a dielectric layer 134 and coupled to conductive lines of the BEOL stacks 106A. The dielectric layer 134 can be dielectric layer 112 as-patterned, or can be a new dielectric layer.

[0055] With reference again to FIGS. 1A and 1B, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a front-end-of-line (FEOL) stack 122 having a surface including first conductive features and first dielectric features. A back-end-of-line (BEOL) stack 106A is coupled to the FEOL stack. The BEOL 106A stack has a surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the surface of the FEOL stack 122, respectively. In one embodiment, the second conductive features are laterally offset from the corresponding first conductive features, such as described in association with FIG. 1C.

[0056] In one embodiment, the first and second conductive features include copper, and the first and second dielectric features include silicon and oxygen. In one embodiment, the FEOL stack 122 includes gate-all-around-based devices. In one embodiment, the FEOL stack 122 includes fin-based devices. In one embodiment, the structure further includes a backside stack having a surface in contact with a surface of the FEOL stack 122, such as is described in association with FIGS. 1D and 1E. It is to be appreciated that although many embodiments involve split processing of front end and backend layers, other embodiments can include a split between front end with a lower backend layer and a structure including upper backend layer(s), depending on the application.

[0057] With reference again to FIGS. 1A and 1B as a general overview, it is to be appreciated that several arrangements are possible. In one embodiment, wafer 1/wafer 2 can be bonded either with wafer to wafer or chip to wafer bonding schemes. In one embodiment, for wafer to wafer bonding, fiducials are placed at frame. In one embodiment, for chip to wafer bonding, fiducials are included within die. In one embodiment, additional singulation and passivation operations are included. In one embodiment, BE layers in wafer 2 can be grown in a conventional method from small to large pitches. In one embodiment, the scheme uses CW bonding, and silicon grinding to flip the layer, as illustrated in FIGS. 1A and 1B. In one embodiment, BE layers in wafer 2 can be grown in reverse order from large pitch to small pitch, which can eliminate a carrier wafer bonding operation from the schemes of FIGS. 1A and 1B. Such a scheme can lead to a carrier layer located in reverse in comparison to conventional BE processing, which can be detected with FA. In one embodiment, backside power layers can be used for bonding, such as described below in association with FIGS. 1D and 1E. In such a case, front end, backend, and backside power layers can constitute three different wafers and involve three different bonding operations. In one embodiment, the bonding layers are located between, but not limited to the front end/backend boundaries. For instance, the bonding layers can be formed within EUV or DUV layers in the BE stack, depending on the bonding accuracy availability. In one embodiment, a bonding dielectric can be an oxide (e.g., silicon oxide), or other dielectric material(s) including oxynitride, SiCN, SiN, etc. In one embodiment, for metal-to-metal bonding, copper (Cu) is used, but bonding between different types of metals can also be used. FIG. 1C, described below, is illustrative of bonding using oxide as the dielectric layers, and Cu as the metal-to-metal bonding. In one embodiment, a process scheme described herein allows different dies within the same reticle by bonding different FE/BE stacks over different dies. In one embodiment, a scheme described herein also allows different BE routing for the same FE stacks within the same SOC design, which enables different routing requirements with the same FE designs.

[0058] With reference again to FIGS. 1A and 1B as a general overview, in accordance with an embodiment of the present disclosure, a fabrication flow includes independent processing of two different wafers with front end (wafer 1) and backend (wafer 2). In one embodiment, when processing wafer 2 with BE layers, BE layers are processed from small pitch to large, which leaves bulk silicon under the lowest pitch layer. In one embodiment, in order to enable the bonding, a carrier wafer is first attached and original bulk silicon is removed before bonding. In one embodiment, the bonding layers are between front end/backend boundary. In one embodiment, the bonding is initiated between a dielectric film, and additional cure process promote the bonding between metal layers. In one embodiment, high accuracy bonding is used to attach wafer 1 and wafer 2 without excess overlay error. In one embodiment, once the bonding is completed, a silicon carrier wafer over wafer 2 is removed before the bump layers can be added to enable SORT/class testing for yield learning.

[0059] It is to be appreciated that bonded structures described herein may be slightly laterally offset from one another as a result of the bonding process. Such an offset can appear as an artifact of a resulting structure. As an example, FIG. 1C illustrates a cross-sectional view of a structure 140 composed of two bonded portions 142 and 144, in accordance with an embodiment of the present disclosure.

[0060] Referring to FIG. 1C, an upper substrate or wafer 142 includes a carrier substrate 148, over conductive lines and vias 142A, 142B, 142C in one or more dielectric layers 145. A lower substrate or wafer 144 includes a carrier or dielectric layer below a stack of device and/or metallization layers 144A, 144B, 144C, 144D, 144E in one or more dielectric layers 145. An interface 146 is between the two bonded portions 142 and 144. The interface 146 can include regions or metal-to-metal bonding, dielectric-to-dielectric bonding, or both. In one embodiment, the two bonded portions 142 and 144 are slightly laterally offset from one another. For example, as shown, a conductive feature 144E is bonded to and in contact with an overlying similar feature, but the features are laterally offset from one another, e.g., as depicted by the offset in their corresponding central vertical axes 147A and 147B.

[0061] As an exemplary process, FIGS. 1D-1E illustrate cross-sectional views representing various operations in a method in which three independent wafers are generated for front end and backside power layers, in accordance with an embodiment of the present disclosure.

[0062] Referring to part (a) of FIG. 1D, a starting structure 150 (which can be referred to as a wafer 2 structure) includes a carrier wafer or substrate 152, such as a silicon wafer or substrate. A back-end-of-line (BEOL) stack 154 is on the carrier wafer or substrate 152. The BEOL stack 154 includes one or more layers of conductive lines and vias, which can be referred to as metallization layers, e.g., in a surrounding dielectric layer or stack of dielectric layers. A dielectric layer 156, such as a silicon oxide or silicon dioxide layer, is on the BEOL stack 154.

[0063] Referring again to part (a) of FIG. 1D, a starting structure 158 (which can be referred to as a wafer 1 structure) includes a carrier wafer or substrate 160, such as a silicon wafer or substrate. A dielectric layer 162, such as a silicon oxide or silicon dioxide layer, is on the carrier wafer or substrate 160. A front-end-of-line (FEOL) stack 164 is on the dielectric layer 162. The FEOL stack 164 includes one or more layers of devices, such as complementary metal oxide semiconductor (CMOS) devices, and one or more layers of device contacts, e.g., in a surrounding dielectric layer or stack of dielectric layers.

[0064] Referring to part (b) of FIG. 1D, the carrier wafer or substrate 152 is removed from the starting structure 150. The resulting structure is bonded to the starting structure 158 to form a unified structure 166. In one embodiment, the unified structure 166 is achieved using metal-to-metal bonding between the starting structure 158 and the BEOL stack 154. In one embodiment, the unified structure 166 is achieved using dielectric-to-dielectric bonding between the starting structure 158 and the BEOL stack 154. In one embodiment, the unified structure 166 is achieved using both metal-to-metal bonding and dielectric-to-dielectric bonding between the starting structure 158 and the BEOL stack 154. It is to be appreciated that for hybrid bonding, both metal-to-metal bonding and dielectric-to-dielectric bonding are employed.

[0065] Referring to part (c) of FIG. 1E, unified structure 166 is shown above a starting structure 168 (which can be referred to as a wafer 3 structure). Starting structure 168 includes a carrier wafer or substrate 170, such as a silicon wafer or substrate. A back-end-of-line (BEOL) stack 172 is on the carrier wafer or substrate 170. The BEOL stack 172 includes one or more layers of conductive lines and vias, which can be referred to as metallization layers, e.g., in a surrounding dielectric layer or stack of dielectric layers. A dielectric layer 174, such as a silicon oxide or silicon dioxide layer, is on the BEOL stack 172.

[0066] Referring to part (d) of FIG. 1E, the carrier wafer or substrate 170 is removed from the starting structure 168 and the resulting structure is inverted to include inverted BEOL stack 172A. The carrier wafer or substrate 160 and the dielectric layer 162 are removed from the starting structure 166. The remaining structures are bonded together to form a unified structure. In one embodiment, the unified structure is achieved using metal-to-metal bonding between the FEOL stack 164 and the BEOL stack 172. In one embodiment, the unified structure is achieved using dielectric-to-dielectric bonding between the FEOL stack 164 and the BEOL stack 172. In one embodiment, the unified structure is achieved using both metal-to-metal bonding and dielectric-to-dielectric bonding between the FEOL stack 164 and the BEOL stack 172. An integrated circuit structure 180 can be formed to include backside conductive bumps 176 on a dielectric layer 174A and coupled to conductive lines of the BEOL stacks 172A. The dielectric layer 174A can be dielectric layer 174 as-patterned, or can be a new dielectric layer. Front side conductive bumps can also be formed to contact BEOL stack 154.

[0067] With reference again to FIGS. 1A and 1B, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a front-end-of-line (FEOL) stack 164 having a surface including first conductive features and first dielectric features. A backside stack 172A is coupled to the FEOL stack 164. The backside stack 172A has a surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the surface of the FEOL stack 164, respectively. In one embodiment, the second conductive features are laterally offset from the corresponding first conductive features, such as described in association with FIG. 1C.

[0068] In one embodiment, the first and second conductive features include copper, and the first and second dielectric features include silicon and oxygen. In one embodiment, the FEOL stack 164 includes gate-all-around-based devices. In one embodiment, the FEOL stack 164 includes fin-based devices. In one embodiment, the structure further includes a front-end-of-line (FEOL) stack 154 having a surface in contact with a surface of the FEOL stack 164.

[0069] To provide further context for the process described in association with FIGS. 1D-1E, traditionally, power is delivered from a front side interconnect. At standard cell level, power can be delivered right on top of transistors or from a top and bottom cell boundary. Power delivered from a top and bottom cell boundary enables relatively shorter standard cell height with slightly higher power network resistance. However, a front side power network shares interconnect stack with signal routing and reduces signal routing tracks. In addition, for high performance design, top and bottom cell boundary power metal wires must be wide enough to reduce power network resistance and improve performance. This normally results in a cell height increase. In accordance with one or more embodiments of the present disclosure, delivering power from a wafer or substrate backside can be implemented to solve area and performance problems. At the cell level, wider metal 0 power at the top and bottom cell boundary may no longer be needed and, hence, cell height can be reduced. In addition, power network resistance can be significantly reduced resulting in performance improvement. At block and chip level, front side signal routing tracks are increased due to removed power routing and power network resistance is significantly reduced due to very wide wires, large vias and reduced interconnect layers.

[0070] In earlier technologies, a power delivery network from bump to the transistor required significant block resources. Such resource usage on the metal stack expressed itself in some process nodes as Standard Cell architectures with layout versioning or cell placement restrictions in the block level. In an embodiment, eliminating the power delivery network from the front side metal stack allows free sliding cell placement in the block without power delivery complications and placement related delay timing variation.

[0071] As a comparison, FIG. 2 illustrates cross-sectional views of an interconnect stack having front side power delivery and of an interconnect stack having backside power delivery, in accordance with an embodiment of the present disclosure.

[0072] Referring to FIG. 2, an interconnect stack 200 having front side power delivery includes a transistor 202 and signal and power delivery metallization 204. The transistor 202 includes a bulk substrate 206, semiconductor fins 208, a terminal 210, and a device contact 212. The signal and power delivery metallization 204 includes conductive vias 214, conductive lines 216, and a metal bump 218.

[0073] Referring again to FIG. 2, an interconnect stack 250 having backside power delivery includes a transistor 252, front side signal metallization 254A, and power delivery metallization 254B. The transistor 252 includes semiconductor nanowires or nanoribbons 258, a terminal 260, and a device contact 262, and a boundary deep via 263. The front side signal metallization 254A includes conductive vias 264A and conductive lines 266A. The power delivery metallization 254B includes conductive vias 264B, conductive lines 266B, and a metal bump 268.

[0074] To provide further context, one of the ultimate goals in Standard Cell design is to minimize the impact of the power delivery to the signal routing in terms of area, while maintaining a robust power delivery scheme which would have minimum voltage drop from the supply. With front side power delivery, commercialized Standard Cell architectures had to allocate routing tracks for power and ground from the top of the front side stack to the first metal routing layer, MO. This approach would exploit metal routing tracks. That means tighter metal pitches are required to deliver power while routing signals. Tighter metal pitches cause higher cap and resistance resulting in higher power consumption. Furthermore, due to the resistance greater voltage drop occurs from the top of the stack to the transistor source.

[0075] In another aspect, direct power connection is made to a backside with through a deep via structure or backside contact. Power gating is performed in the front-end. As an exemplary structure, FIG. 3 illustrates a cross-sectional view of an integrated circuit structure having a nanowire layer and backside power delivery, in accordance with an embodiment of the present disclosure. It is to be appreciated that although nanowires (or nanoribbons or nanosheets) are depicted in FIG. 3, a fin-based architecture or a planar architecture can also be used.

[0076] Referring to FIG. 3, an integrated circuit structure 300 includes a front side structure 304 on a backside structure 302. The front side structure 304 includes a device layer 306, and a plurality of metallization layers 308 on the device layer 306. The structure 300 may be supported by a carrier wafer 310 on the front side structure 304. The backside structure 302 includes a stack of backside conductive structures that terminate at a conductive bump 312. In one embodiment, upper ones of the metallization layers 308 (e.g., above metal 0) or all of the metallization layers 308 are formed as a separate BEOL wafer or chip, and the device layer 306 and lower ones of the metallization layers (e.g., metal 0) or just the device layer are/is formed as a separate FEOL wafer or chip.

[0077] In an embodiment, the device layer 306 includes Field Effect Transistors (FETs), such as nanowire-based (shown) or fin-based transistors. In one such, embodiment, the FETs are used for memory. In an embodiment, the device layer 306 further includes trench contacts (TCN), gate contacts (GCN) and contact vias (VCX). In an embodiment, the device layer 306 is on a deep via (DV) layer of the front side structure 304, as is depicted. In an embodiment, the plurality of metallization layers 308 includes increasing metal layer (e.g., M0-M12) and associated via layers (e.g., V0-V3 called out in FIG. 3).

[0078] In an embodiment, the backside structure 302 includes a plurality of backside metal layers (e.g., BM0-BM3) and associated vias. In an embodiment, the backside structure 302 includes one or more power structures, such as ground metal lines (e.g., GMO and GM1). In an embodiment, the backside structure 302 includes one or more capacitor structures, such as a metal-insulator-metal (MIM) capacitor). In one embodiment, the lower ones of the backside metal layers (e.g., below BM0) or all of the backside metal layers (e.g., BM0-BM3) are formed as a separate wafer or chip.

[0079] In another aspect, the above described metallization structures or stacks can be fabricated above or bonded to underlying or overlying device layers. Such device layers can be or include gate-all-around device layers, or FinFET layers, or planar device layers.

[0080] It is to be appreciated that, in a particular embodiment, nanowires or nanoribbons, or fins, or sacrificial intervening layers, may be composed of silicon. As used throughout, a silicon layer may be used to describe a silicon material composed of a very substantial amount of, if not all, silicon. However, it is to be appreciated that, practically, 100% pure Si may be difficult to form and, hence, could include a tiny percentage of carbon, germanium or tin. Such impurities may be included as an unavoidable impurity or component during deposition of Si or may contaminate the Si upon diffusion during post deposition processing. As such, embodiments described herein directed to a silicon layer may include a silicon layer that contains a relatively small amount, e.g., impurity level, non-Si atoms or species, such as Ge, C or Sn. It is to be appreciated that a silicon layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic.

[0081] It is to be appreciated that, in a particular embodiment, nanowires or nanoribbons, or fins, or sacrificial intervening layers, may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material composed of substantial portions of both silicon and germanium, such as at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In particular embodiments, a silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si.sub.40Ge.sub.60). In other embodiments, the amount of silicon is greater than the amount of germanium. In particular embodiments, a silicon germanium layer includes approximately 30% germanium and approximately 70% silicon (Si.sub.70Ge.sub.30). It is to be appreciated that, practically, 100% pure silicon germanium (referred to generally as SiGe) may be difficult to form and, hence, could include a tiny percentage of carbon or tin. Such impurities may be included as an unavoidable impurity or component during deposition of SiGe or may contaminate the SiGe upon diffusion during post deposition processing. As such, embodiments described herein directed to a silicon germanium layer may include a silicon germanium layer that contains a relatively small amount, e.g., impurity level, non-Ge and non-Si atoms or species, such as carbon or tin. It is to be appreciated that a silicon germanium layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic.

[0082] It is to be appreciated that the embodiments described herein can also include other implementations such as nanowires and/or nanoribbons and/or fins with various widths, thicknesses and/or materials including but not limited to Si and SiGe. For example, group III-V materials may be used.

[0083] Described below are various devices and processing schemes that may be used to fabricate a device. It is to be appreciated that the exemplary embodiments need not necessarily require all features described, or may include more features than are described. For example, nanowire release processing may be performed through a replacement gate trench. Examples of such release processes are described below. Additionally, in yet another aspect, backend (BE) interconnect scaling can result in lower performance and higher manufacturing cost due to patterning complexity. Embodiments described herein may be implemented to enable front side and backside interconnect integration for nanowire transistors. Embodiments described herein may provide an approach to achieve a relatively wider interconnect pitch. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0084] One or more embodiments described herein are directed dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire/nanoribbon transistors which are partially filled with SD epitaxy. A remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain side enables direct contact to a backside interconnect level.

[0085] As an exemplary process flow for fabricating a gate-all-around device of a gate-all-around integrated circuit structure, FIGS. 4A-4J illustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure.

[0086] Referring to FIG. 4A, a method of fabricating an integrated circuit structure includes forming a starting stack which includes alternating sacrificial layers 404 and nanowires 406 above a fin 402, such as a silicon fin. The nanowires 406 may be referred to as a vertical arrangement of nanowires. A protective cap 408 may be formed above the alternating sacrificial layers 404 and nanowires 406, as is depicted. A relaxed buffer layer 452 and a defect modification layer 450 may be formed beneath the alternating sacrificial layers 404 and nanowires 406, as is also depicted.

[0087] Referring to FIG. 4B, a gate stack 410 is formed over the vertical arrangement of horizontal nanowires 406. Portions of the vertical arrangement of horizontal nanowires 406 are then released by removing portions of the sacrificial layers 404 to provide recessed sacrificial layers 404and cavities 412, as is depicted in FIG. 4C.

[0088] It is to be appreciated that the structure of FIG. 4C may be fabricated to completion without first performing the deep etch and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), in an embodiment, a fabrication process involves use of a process scheme that provides a gate-all-around integrated circuit structure having epitaxial nubs, which may be vertically discrete source or drain structures.

[0089] Referring to FIG. 4D, upper gate spacers 414 are formed at sidewalls of the gate structure 410. Cavity spacers 416 are formed in the cavities 412 beneath the upper gate spacers 414. A deep trench contact etch is then optionally performed to form trenches 418 and to form recessed nanowires 406. A patterned relaxed buffer layer 452 and a patterned defect modification layer 450may also be present, as is depicted.

[0090] A sacrificial material 420 is then formed in the trenches 418, as is depicted in FIG. 4E. In other process schemes, an isolated trench bottom or silicon trench bottom may be used.

[0091] Referring to FIG. 4F, a first epitaxial source or drain structure (e.g., left-hand features 422) is formed at a first end of the vertical arrangement of horizontal nanowires 406. A second epitaxial source or drain structure (e.g., right-hand features 422) is formed at a second end of the vertical arrangement of horizontal nanowires 406. In an embodiment, as depicted, the epitaxial source or drain structures 422 are vertically discrete source or drain structures and may be referred to as epitaxial nubs. In other embodiments, the epitaxial source or drain structures 422 are vertically non-discrete source or drain structures where a single merged structure is in place of a plurality of nubs.

[0092] An inter-layer dielectric (ILD) material 424 is then formed at the sides of the gate electrode 410 and adjacent the source or drain structures 422, as is depicted in FIG. 4G. Referring to FIG. 4H, a replacement gate process is used to form a permanent gate dielectric 428 and a permanent gate electrode 426. The ILD material 424 is then removed, as is depicted in FIG. 4I. The sacrificial material 420 is then removed from one of the source drain locations (e.g., right-hand side) to form trench 432, but is not removed from the other of the source drain locations to form trench 430.

[0093] Referring to FIG. 4J, a first conductive contact structure 434 is formed coupled to the first epitaxial source or drain structure (e.g., left-hand features 422). A second conductive contact structure 436 is formed coupled to the second epitaxial source or drain structure (e.g., right-hand features 422). The second conductive contact structure 436 is formed deeper along the fin 402 than the first conductive contact structure 434. In an embodiment, although not depicted in FIG. 4J, the method further includes forming an exposed surface of the second conductive contact structure 436 at a bottom of the fin 402. Conductive contacts may include a contact resistance reducing layer and a primary contact electrode layer, where examples can include Ti, Ni, Co (for the former and W, Ru, Co for the latter.)

[0094] In an embodiment, the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434, as is depicted. In one such embodiment, the first conductive contact structure 434 is not along the fin 402, as is depicted. In another such embodiment, not depicted, the first conductive contact structure 434 is partially along the fin 402.

[0095] In an embodiment, the second conductive contact structure 436 is along an entirety of the fin 402. In an embodiment, although not depicted, in the case that the bottom of the fin 402 is exposed by a backside substrate removal process, the second conductive contact structure 436 has an exposed surface at a bottom of the fin 402.

[0096] In another aspect, in order to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, integrated circuit structures described herein may be fabricated using a backside reveal of front side structures fabrication approach. In some exemplary embodiments, reveal of the backside of a transistor or other device structure entails wafer-level backside processing. In contrast to a conventional TSV-type technology, a reveal of the backside of a transistor as described herein may be performed at the density of the device cells, and even within sub-regions of a device. Furthermore, such a reveal of the backside of a transistor may be performed to remove substantially all of a donor substrate upon which a device layer was disposed during front side device processing. As such, a microns-deep TSV becomes unnecessary with the thickness of semiconductor in the device cells following a reveal of the backside of a transistor potentially being only tens or hundreds of nanometers.

[0097] Reveal techniques described herein may enable a paradigm shift from bottom-up device fabrication to center-out fabrication, where the center is any layer that is employed in front side fabrication, revealed from the backside, and again employed in backside fabrication. Processing of both a front side and revealed backside of a device structure may address many of the challenges associated with fabricating 3D ICs when primarily relying on front side processing.

[0098] A reveal of the backside of a transistor approach may be employed for example to remove at least a portion of a carrier layer and intervening layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a carrier layer in the donor-host substrate is polished (e.g., CMP) and/or etched with a wet or dry (e.g., plasma) etch process. Any grind, polish, and/or wet/dry etch process known to be suitable for the composition of the carrier layer may be employed. For example, where the carrier layer is a group IV semiconductor (e.g., silicon) a CMP slurry known to be suitable for thinning the semiconductor may be employed. Likewise, any wet etchant or plasma etch process known to be suitable for thinning the group IV semiconductor may also be employed.

[0099] In some embodiments, the above is preceded by cleaving the carrier layer along a fracture plane substantially parallel to the intervening layer. The cleaving or fracture process may be utilized to remove a substantial portion of the carrier layer as a bulk mass, reducing the polish or etch time needed to remove the carrier layer. For example, where a carrier layer is 400-900 m in thickness, 100-700 m may be cleaved off by practicing any blanket implant known to promote a wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the carrier layer where the fracture plane is desired. Following such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly may then be polished or etched to complete removal. Alternatively, where the carrier layer is not fractured, the grind, polish and/or etch operation may be employed to remove a greater thickness of the carrier layer.

[0100] Next, exposure of an intervening layer is detected. Detection is used to identify a point when the backside surface of the donor substrate has advanced to nearly the device layer. Any endpoint detection technique known to be suitable for detecting a transition between the materials employed for the carrier layer and the intervening layer may be practiced. In some embodiments, one or more endpoint criteria are based on detecting a change in optical absorbance or emission of the backside surface of the donor substrate during the polishing or etching performance. In some other embodiments, the endpoint criteria are associated with a change in optical absorbance or emission of byproducts during the polishing or etching of the donor substrate backside surface. For example, absorbance or emission wavelengths associated with the carrier layer etch byproducts may change as a function of the different compositions of the carrier layer and intervening layer. In other embodiments, the endpoint criteria are associated with a change in mass of species in byproducts of polishing or etching the backside surface of the donor substrate. For example, the byproducts of processing may be sampled through a quadrupole mass analyzer and a change in the species mass may be correlated to the different compositions of the carrier layer and intervening layer. In another exemplary embodiment, the endpoint criteria is associated with a change in friction between a backside surface of the donor substrate and a polishing surface in contact with the backside surface of the donor substrate.

[0101] Detection of the intervening layer may be enhanced where the removal process is selective to the carrier layer relative to the intervening layer as non-uniformity in the carrier removal process may be mitigated by an etch rate delta between the carrier layer and intervening layer. Detection may even be skipped if the grind, polish and/or etch operation removes the intervening layer at a rate sufficiently below the rate at which the carrier layer is removed. If an endpoint criteria is not employed, a grind, polish and/or etch operation of a predetermined fixed duration may stop on the intervening layer material if the thickness of the intervening layer is sufficient for the selectivity of the etch. In some examples, the carrier etch rate: intervening layer etch rate is 3:1-10:1, or more.

[0102] Upon exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. A thickness of the intervening layer may be removed uniformly by a polish, for example. Alternatively, a thickness of the intervening layer may be removed with a masked or blanket etch process. The process may employ the same polish or etch process as that employed to thin the carrier, or may be a distinct process with distinct process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polish or etch process that favors removal of the intervening layer over removal of the device layer. Where less than a few hundred nanometers of intervening layer thickness is to be removed, the removal process may be relatively slow, optimized for across-wafer uniformity, and more precisely controlled than that employed for removal of the carrier layer. A CMP process employed may, for example employ a slurry that offers very high selectivity (e.g., 100:1-300:1, or more) between semiconductor (e.g., silicon) and dielectric material (e.g., SiO) surrounding the device layer and embedded within the intervening layer, for example, as electrical isolation between adjacent device regions.

[0103] For embodiments where the device layer is revealed through complete removal of the intervening layer, backside processing may commence on an exposed backside of the device layer or specific device regions there in. In some embodiments, the backside device layer processing includes a further polish or wet/dry etch through a thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region.

[0104] In some embodiments where the carrier layer, intervening layer, or device layer backside is recessed with a wet and/or plasma etch, such an etch may be a patterned etch or a materially selective etch that imparts significant non-planarity or topography into the device layer backside surface. As described further below, the patterning may be within a device cell (i.e., intra-cell patterning) or may be across device cells (i.e., inter-cell patterning). In some patterned etch embodiments, at least a partial thickness of the intervening layer is employed as a hard mask for backside device layer patterning. Hence, a masked etch process may preface a correspondingly masked device layer etch.

[0105] The above described processing scheme may result in a donor-host substrate assembly that includes IC devices that have a backside of an intervening layer, a backside of the device layer, and/or backside of one or more semiconductor regions within the device layer, and/or front side metallization revealed. Additional backside processing of any of these revealed regions may then be performed during downstream processing.

[0106] It is to be appreciated that the structures resulting from the above exemplary processing schemes may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and/or NMOS device fabrication. As an example of a completed device, FIG. 5 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure.

[0107] Referring to FIG. 5, a semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including protruding fin portion 504 and sub-fin region 505) within a trench isolation region 506. In an embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (such as nanowires 504A and 504B) above sub-fin region 505, as is represented by the dashed lines. In either case, for ease of description for non-planar integrated circuit structure 500, a non-planar active region 504 is referenced below as a protruding fin portion. In an embodiment, the sub-fin region 505 also includes a relaxed buffer layer 542 and a defect modification layer 540, as is depicted.

[0108] A gate line 508 is disposed over the protruding portions 504 of the non-planar active region (including, if applicable, surrounding nanowires 504A and 504B), as well as over a portion of the trench isolation region 506. As shown, gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, gate line 508 may also include a dielectric cap layer 554. A gate contact 514, and overlying gate contact via 516 are also seen from this perspective, along with an overlying metal interconnect 560, all of which are disposed in inter-layer dielectric stacks or layers 570. Also seen from the perspective of FIG. 5, the gate contact 514 is, in one embodiment, disposed over trench isolation region 506, but not over the non-planar active regions. In another embodiment, the gate contact 514 is over the non-planar active regions.

[0109] In an embodiment, the semiconductor structure or device 500 is a non-planar device such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 508 surround at least a top surface and a pair of sidewalls of the three-dimensional body.

[0110] As is also depicted in FIG. 5, in an embodiment, an interface 580 exists between a protruding fin portion 504 and sub-fin region 505. The interface 580 can be a transition region between a doped sub-fin region 505 and a lightly or undoped upper fin portion 504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and sub-fin dopants are optionally supplied from an adjacent solid state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0111] Although not depicted in FIG. 5, it is to be appreciated that source or drain regions of or adjacent to the protruding fin portions 504 are on either side of the gate line 508, i.e., into and out of the page. In one embodiment, the material of the protruding fin portions 504 in the source or drain locations is removed and replaced with another semiconductor material, e.g., by epitaxial deposition to form epitaxial source or drain structures. The source or drain regions may extend below the height of dielectric layer of trench isolation region 506, i.e., into the sub-fin region 505. In accordance with an embodiment of the present disclosure, the more heavily doped sub-fin regions, i.e., the doped portions of the fins below interface 580, inhibits source to drain leakage through this portion of the bulk semiconductor fins. In an embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above in association with FIG. 4J.

[0112] With reference again to FIG. 5, in an embodiment, fins 504/505 (and, possibly nanowires 504A and 504B) are composed of a crystalline silicon germanium layer which may be doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof.

[0113] In an embodiment, trench isolation region 506, and trench isolation regions (trench isolations structures or trench isolation layers) described throughout, may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, trench isolation region 506 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

[0114] Gate line 508 may be composed of a gate electrode stack which includes a gate dielectric layer 552 and a gate electrode layer 550. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 552 is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer 552 may include a layer of native oxide formed from the top few layers of the substrate fin 504. In an embodiment, the gate dielectric layer 552 is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 552 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

[0115] In one embodiment, the gate electrode layer 550 is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode layer 550 is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer 550 may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer 550 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0116] Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

[0117] Gate contact 514 and overlying gate contact via 516 may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

[0118] In an embodiment (although not shown), a contact pattern which is essentially perfectly aligned to an existing gate pattern 508 is formed while eliminating the use of a lithographic operation with exceedingly tight registration budget. In an embodiment, the contact pattern is a vertically symmetric contact pattern, or an asymmetric contact pattern such as described in association with FIG. 4J. In other embodiments, all contacts are front side connected and are not asymmetric. In one such embodiment, the self-aligned approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

[0119] In an embodiment, providing structure 500 involves fabrication of the gate stack structure 508 by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF.sub.6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH.sub.4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

[0120] Referring again to FIG. 5, the arrangement of semiconductor structure or device 500 places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region, e.g., over a fin 505, and in a same layer as a trench contact via.

[0121] It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a sub-10 nanometer (10 nm) technology node.

[0122] In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO.sub.2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0123] In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

[0124] In an embodiment, as is also used throughout the present description, hardmask materials, capping layers, or plugs are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask, capping or plug materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer, capping or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Other hardmask, capping or plug layers known in the arts may be used depending upon the particular implementation. The hardmask, capping or plug layers maybe formed by CVD, PVD, or by other deposition methods.

[0125] In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion lithography (i193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a tri-layer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

[0126] In another aspect, a pitch quartering approach is implemented for patterning trenches in a dielectric layer (permanent or sacrificial) for forming BEOL interconnect structures or for directly patterning metal features in a subtractive approach. In accordance with an embodiment of the present disclosure, pitch division is applied for fabricating metal lines in a BEOL fabrication scheme. Embodiments may enable continued scaling of the pitch of metal layers beyond the resolution capability of state-of-the art lithography equipment.

[0127] FIG. 6 is a schematic of a pitch quartering approach 600 used to fabricate trenches for interconnect structures, in accordance with an embodiment of the present disclosure.

[0128] Referring to FIG. 6, at operation (a), backbone features 602 are formed using direct lithography. For example, a photoresist layer or stack may be patterned and the pattern transferred into a hardmask material to ultimately form backbone features 602. The photoresist layer or stack used to form backbone features 602 may be patterned using standard lithographic processing techniques, such as 193 immersion lithography. First spacer features 604 are then formed adjacent the sidewalls of the backbone features 602.

[0129] At operation (b), the backbone features 602 are removed to leave only the first spacer features 604 remaining. At this stage, the first spacer features 604 are effectively a half pitch mask, e.g., representing a pitch halving process. The first spacer features 604 can either be used directly for a pitch quartering process, or the pattern of the first spacer features 604 may first be transferred into a new hardmask material, where the latter approach is depicted.

[0130] At operation (c), the pattern of the first spacer features 604 transferred into a new hardmask material to form first spacer features 604. Second spacer features 606 are then formed adjacent the sidewalls of the first spacer features 604.

[0131] At operation (d), the first spacer features 604are removed to leave only the second spacer features 606 remaining. At this stage, the second spacer features 606 are effectively a quarter pitch mask, e.g., representing a pitch quartering process.

[0132] At operation (e), the second spacer features 606 are used as a mask to pattern a plurality of trenches 608 in a dielectric or hardmask layer. The trenches may ultimately be filled with conductive material to form conductive interconnects in metallization layers of an integrated circuit. Trenches 608 having the label B correspond to backbone features 602. Trenches 608 having the label S correspond to first spacer features 604 or 604. Trenches 608 having the label C correspond to a complementary region 607 between backbone features 602.

[0133] It is to be appreciated that since individual ones of the trenches 608 of FIG. 6 have a patterning origin that corresponds to one of backbone features 602, first spacer features 604 or 604, or complementary region 607 of FIG. 6, differences in width and/or pitch of such features may appear as artifacts of a pitch quartering process in ultimately formed conductive interconnects in metallization layers of an integrated circuit. As an example, FIG. 7A illustrates a cross-sectional view of a metallization layer fabricated using pitch quartering scheme, in accordance with an embodiment of the present disclosure. It is to be appreciated that a metal layer described in association with FIG. 7A can be used in a process or included in a structure fabricated using split processing of integrated circuit layers with high accuracy bonding, such as is described in association with FIGS. 1A-1E.

[0134] Referring to FIG. 7A, an integrated circuit structure 700 includes an inter-layer dielectric (ILD) layer 704 above a substrate 702. A plurality of conductive interconnect lines 706 is in the ILD layer 704, and individual ones of the plurality of conductive interconnect lines 706 are spaced apart from one another by portions of the ILD layer 704. Individual ones of the plurality of conductive interconnect lines 706 includes a conductive barrier layer 708 and a conductive fill material 710.

[0135] With reference to both FIGS. 6 and 7A, conductive interconnect lines 706B are formed in trenches with a pattern originating from backbone features 602. Conductive interconnect lines 706S are formed in trenches with a pattern originating from first spacer features 604 or 604. Conductive interconnect lines 706C are formed in trenches with a pattern originating from complementary region 607 between backbone features 602.

[0136] Referring again to FIG. 7A, in an embodiment, the plurality of conductive interconnect lines 706 includes a first interconnect line 706B having a width (W1). A second interconnect line 706S is immediately adjacent the first interconnect line 706B, the second interconnect line 706S having a width (W2) different than the width (W1) of the first interconnect line 706B. A third interconnect line 706C is immediately adjacent the second interconnect line 706S, the third interconnect line 706C having a width (W3). A fourth interconnect line (second 706S) immediately adjacent the third interconnect line 706C, the fourth interconnect line having a width (W2) the same as the width (W2) of the second interconnect line 706S. A fifth interconnect line (second 706B) is immediately adjacent the fourth interconnect line (second 706S), the fifth interconnect line (second 706B) having a width (W1) the same as the width (W1) of the first interconnect line 706B.

[0137] In an embodiment, the width (W3) of the third interconnect line 706C is different than the width (W1) of the first interconnect line 706B. In one such embodiment, the width (W3) of the third interconnect line 706C is different than the width (W2) of the second interconnect line 706S. In another such embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W2) of the second interconnect line 706S. In another embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W1) of the first interconnect line 706B.

[0138] In an embodiment, a pitch (P1) between the first interconnect line 706B and the third interconnect line 706C is the same as a pitch (P2) between the second interconnect 706S line and the fourth interconnect line (second 706S). In another embodiment, a pitch (P1) between the first interconnect line 706B and the third interconnect line 706C is different than a pitch (P2) between the second interconnect line 706S and the fourth interconnect line (second 706S).

[0139] Referring again to FIG. 7A, in another embodiment, the plurality of conductive interconnect lines 706 includes a first interconnect line 706B having a width (W1). A second interconnect line 706S is immediately adjacent the first interconnect line 706B, the second interconnect line 706S having a width (W2). A third interconnect line 706C is immediately adjacent the second interconnect line 706S, the third interconnect line 706C having a width (W3) different than the width (W1) of the first interconnect line 706B. A fourth interconnect line (second 706S) is immediately adjacent the third interconnect line 706C, the fourth interconnect line having a width (W2) the same as the width (W2) of the second interconnect line 706S. A fifth interconnect line (second 706B) is immediately adjacent the fourth interconnect line (second 706S), the fifth interconnect line (second 706B) having a width (W1) the same as the width (W1) of the first interconnect line 706B.

[0140] In an embodiment, the width (W2) of the second interconnect line 706S is different than the width (W1) of the first interconnect line 706B. In one such embodiment, the width (W3) of the third interconnect line 706C is different than the width (W2) of the second interconnect line 706S. In another such embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W2) of the second interconnect line 706S.

[0141] In an embodiment, the width (W2) of the second interconnect line 706S is the same as the width (W1) of the first interconnect line 706B. In an embodiment, a pitch (P1) between the first interconnect line 706B and the third interconnect line 706C is the same as a pitch (P2) between the second interconnect line 706S and the fourth interconnect line (second 706S). In an embodiment, a pitch (P1) between the first interconnect line 706B and the third interconnect line 706C is different than a pitch (P2) between the second interconnect line 706S and the fourth interconnect line (second 706S).

[0142] FIG. 7B illustrates a cross-sectional view of a metallization layer fabricated using pitch halving scheme above a metallization layer fabricated using pitch quartering scheme, in accordance with an embodiment of the present disclosure. It is to be appreciated that a metal layer described in association with FIG. 7B can be used in a process or included in a structure fabricated using split processing of integrated circuit layers with high accuracy bonding, such as is described in association with FIGS. 1A-1E.

[0143] Referring to FIG. 7B, an integrated circuit structure 750 includes a first inter-layer dielectric (ILD) layer 754 above a substrate 752. A first plurality of conductive interconnect lines 756 is in the first ILD layer 754, and individual ones of the first plurality of conductive interconnect lines 756 are spaced apart from one another by portions of the first ILD layer 754. Individual ones of the plurality of conductive interconnect lines 756 includes a conductive barrier layer 758 and a conductive fill material 760. The integrated circuit structure 750 further includes a second inter-layer dielectric (ILD) layer 774 above substrate 752. A second plurality of conductive interconnect lines 776 is in the second ILD layer 774, and individual ones of the second plurality of conductive interconnect lines 776 are spaced apart from one another by portions of the second ILD layer 774. Individual ones of the plurality of conductive interconnect lines 776 includes a conductive barrier layer 778 and a conductive fill material 780.

[0144] In accordance with an embodiment of the present disclosure, with reference again to FIG. 7B, a method of fabricating an integrated circuit structure includes forming a first plurality of conductive interconnect lines 756 in and spaced apart by a first inter-layer dielectric (ILD) layer 754 above a substrate 752. The first plurality of conductive interconnect lines 756 is formed using a spacer-based pitch quartering process, e.g., the approach described in association with operations (a)-(e) of FIG. 6. A second plurality of conductive interconnect lines 776 is formed in and is spaced apart by a second ILD layer 774 above the first ILD layer 754. The second plurality of conductive interconnect lines 776 is formed using a spacer-based pitch halving process, e.g., the approach described in association with operations (a) and (b) of FIG. 6.

[0145] In an embodiment, first plurality of conductive interconnect lines 756 has a pitch (P1) between immediately adjacent lines of than 40 nanometers. The second plurality of conductive interconnect lines 776 has a pitch (P2) between immediately adjacent lines of 44 nanometers or greater. In an embodiment, the spacer-based pitch quartering process and the spacer-based pitch halving process are based on an immersion 193 nm lithography process.

[0146] In an embodiment, individual ones of the first plurality of conductive interconnect lines 754 include a first conductive barrier liner 758 and a first conductive fill material 760. Individual ones of the second plurality of conductive interconnect lines 756 include a second conductive barrier liner 778 and a second conductive fill material 780. In one such embodiment, the first conductive fill material 760 is different in composition from the second conductive fill material 780. In another embodiment, the first conductive fill material 760 is the same in composition as the second conductive fill material 780. In an embodiment, the first conductive barrier liner 758 and/or the second conductive barrier liner 778 is a single, nitrogen-free tantalum (Ta) barrier layer.

[0147] Although not depicted, in an embodiment, the method further includes forming a third plurality of conductive interconnect lines in and spaced apart by a third ILD layer above the second ILD layer 774. The third plurality of conductive interconnect lines is formed without using pitch division.

[0148] Although not depicted, in an embodiment, the method further includes, prior to forming the second plurality of conductive interconnect lines 776, forming a third plurality of conductive interconnect lines in and spaced apart by a third ILD layer above the first ILD layer 754. The third plurality of conductive interconnect lines is formed using a spacer-based pitch quartering process. In one such embodiment, subsequent to forming the second plurality of conductive interconnect lines 776, a fourth plurality of conductive interconnect lines is formed in and is spaced apart by a fourth ILD layer above the second ILD layer 774. The fourth plurality of conductive interconnect lines is formed using a spacer-based pitch halving process. In an embodiment, such a method further includes forming a fifth plurality of conductive interconnect lines in and spaced apart by a fifth ILD layer above the fourth ILD layer, the fifth plurality of conductive interconnect lines formed using a spacer-based pitch halving process. A sixth plurality of conductive interconnect lines is then formed in and spaced apart by a sixth ILD layer above the fifth ILD layer, the sixth plurality of conductive interconnect lines formed using a spacer-based pitch halving process. A seventh plurality of conductive interconnect lines is then formed in and spaced apart by a seventh ILD layer above the sixth ILD layer. The seventh plurality of conductive interconnect lines is formed without using pitch division.

[0149] In another aspect, metal line compositions vary between metallization layers. Such an arrangement may be referred to as heterogeneous metallization layers. In an embodiment, copper is used as a conductive fill material for relatively larger interconnect lines, while cobalt is used as a conductive fill material for relatively smaller interconnect lines. The smaller lines having cobalt as a fill material may provide reduced electromigration while maintaining low resistivity. The use of cobalt in place of copper for smaller interconnect lines may address issues with scaling copper lines, where a conductive barrier layer consumes a greater amount of an interconnect volume and copper is reduced, essentially hindering advantages normally associated with a copper interconnect line.

[0150] In a first example, FIG. 8A illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition above a metallization layer with a differing metal line composition, in accordance with an embodiment of the present disclosure. It is to be appreciated that one or more of the interconnects or layers of interconnects described in association with FIG. 8A can be used in a process or included in a structure fabricated using split processing of integrated circuit layers with high accuracy bonding, such as is described in association with FIGS. 1A-1E.

[0151] Referring to FIG. 8A, an integrated circuit structure 800 includes a first plurality of conductive interconnect lines 806 in and spaced apart by a first inter-layer dielectric (ILD) layer 804 above a substrate 802. One of the conductive interconnect lines 806A is shown as having an underlying via 807. Individual ones of the first plurality of conductive interconnect lines 806 include a first conductive barrier material 808 along sidewalls and a bottom of a first conductive fill material 810.

[0152] A second plurality of conductive interconnect lines 816 is in and spaced apart by a second ILD layer 814 above the first ILD layer 804. One of the conductive interconnect lines 816A is shown as having an underlying via 817. Individual ones of the second plurality of conductive interconnect lines 816 include a second conductive barrier material 818 along sidewalls and a bottom of a second conductive fill material 820. The second conductive fill material 820 is different in composition from the first conductive fill material 810. In an embodiment, the second conductive barrier material 818 is a single, nitrogen-free tantalum (Ta) barrier layer.

[0153] In an embodiment, the second conductive fill material 820 consists essentially of copper, and the first conductive fill material 810 consists essentially of cobalt. In one such embodiment, the first conductive barrier material 808 is different in composition from the second conductive barrier material 818. In another such embodiment, the first conductive barrier material 808 is the same in composition as the second conductive barrier material 818.

[0154] In an embodiment, the first conductive fill material 810 includes copper having a first concentration of a dopant impurity atom, and the second conductive fill material 820 includes copper having a second concentration of the dopant impurity atom. The second concentration of the dopant impurity atom is less than the first concentration of the dopant impurity atom. In one such embodiment, the dopant impurity atom is selected from the group consisting of aluminum (Al) and manganese (Mn). In an embodiment, the first conductive barrier material 810 and the second conductive barrier material 820 have the same composition. In an embodiment, the first conductive barrier material 810 and the second conductive barrier material 820 have a different composition.

[0155] Referring again to FIG. 8A, the second ILD layer 814 is on an etch-stop layer 822. The conductive via 817 is in the second ILD layer 814 and in an opening of the etch-stop layer 822. In an embodiment, the first and second ILD layers 804 and 814 include silicon, carbon and oxygen, and the etch-stop layer 822 includes silicon and nitrogen. In an embodiment, individual ones of the first plurality of conductive interconnect lines 806 have a first width (W1), and individual ones of the second plurality of conductive interconnect lines 816 have a second width (W2) greater than the first width (W1).

[0156] In a second example, FIG. 8B illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition coupled to a metallization layer with a differing metal line composition, in accordance with an embodiment of the present disclosure. It is to be appreciated that one or more of the interconnects or layers of interconnects described in association with FIG. 8B can be used in a process or included in a structure fabricated using split processing of integrated circuit layers with high accuracy bonding, such as is described in association with FIGS. 1A-1E.

[0157] Referring to FIG. 8B, an integrated circuit structure 850 includes a first plurality of conductive interconnect lines 856 in and spaced apart by a first inter-layer dielectric (ILD) layer 854 above a substrate 852. One of the conductive interconnect lines 856A is shown as having an underlying via 857. Individual ones of the first plurality of conductive interconnect lines 856 include a first conductive barrier material 858 along sidewalls and a bottom of a first conductive fill material 860.

[0158] A second plurality of conductive interconnect lines 866 is in and spaced apart by a second ILD layer 864 above the first ILD layer 854. One of the conductive interconnect lines 866A is shown as having an underlying via 867. Individual ones of the second plurality of conductive interconnect lines 866 include a second conductive barrier material 868 along sidewalls and a bottom of a second conductive fill material 870. The second conductive fill material 870 is different in composition from the first conductive fill material 860. In an embodiment, the second conductive barrier material 868 is a single, nitrogen-free tantalum (Ta) barrier layer.

[0159] In an embodiment, the conductive via 867 is on and electrically coupled to an individual one 856B of the first plurality of conductive interconnect lines 856, electrically coupling the individual one 866A of the second plurality of conductive interconnect lines 866 to the individual one 856B of the first plurality of conductive interconnect lines 856. In an embodiment, individual ones of the first plurality of conductive interconnect lines 856 are along a first direction 898 (e.g., into and out of the page), and individual ones of the second plurality of conductive interconnect lines 866 are along a second direction 899 orthogonal to the first direction 898, as is depicted. In an embodiment, the conductive via 867 includes the second conductive barrier material 868 along sidewalls and a bottom of the second conductive fill material 870, as is depicted.

[0160] In an embodiment, the second ILD layer 864 is on an etch-stop layer 872 on the first ILD layer 854. The conductive via 867 is in the second ILD layer 864 and in an opening of the etch-stop layer 872. In an embodiment, the first and second ILD layers 854 and 864 include silicon, carbon and oxygen, and the etch-stop layer 872 includes silicon and nitrogen. In an embodiment, individual ones of the first plurality of conductive interconnect lines 856 have a first width (W1), and individual ones of the second plurality of conductive interconnect lines 866 have a second width (W2) greater than the first width (W1).

[0161] In an embodiment, the second conductive fill material 870 consists essentially of copper, and the first conductive fill material 860 consists essentially of cobalt. In one such embodiment, the first conductive barrier material 858 is different in composition from the second conductive barrier material 868. In another such embodiment, the first conductive barrier material 858 is the same in composition as the second conductive barrier material 868.

[0162] In an embodiment, the first conductive fill material 860 includes copper having a first concentration of a dopant impurity atom, and the second conductive fill material 870 includes copper having a second concentration of the dopant impurity atom. The second concentration of the dopant impurity atom is less than the first concentration of the dopant impurity atom. In one such embodiment, the dopant impurity atom is selected from the group consisting of aluminum (Al) and manganese (Mn). In an embodiment, the first conductive barrier material 860 and the second conductive barrier material 870 have the same composition. In an embodiment, the first conductive barrier material 860 and the second conductive barrier material 870 have a different composition.

[0163] FIGS. 9A-9C illustrate cross-section views of individual interconnect lines having various barrier liner and conductive capping structural arrangements suitable for the structures described in association with FIGS. 8A and 8B, in accordance with an embodiment of the present disclosure.

[0164] Referring to FIG. 9A, an interconnect line 900 in a dielectric layer 901 includes a conductive barrier material 902 and a conductive fill material 904. The conductive barrier material 902 includes an outer layer 906 distal from the conductive fill material 904 and an inner layer 908 proximate to the conductive fill material 904. In an embodiment, the conductive fill material includes cobalt, the outer layer 906 includes titanium and nitrogen, and the inner layer 908 includes tungsten, nitrogen and carbon. In one such embodiment, the outer layer 906 has a thickness of approximately 2 nanometers, and the inner layer 908 has a thickness of approximately 0.5 nanometers. In another embodiment, the conductive fill material includes cobalt, the outer layer 906 includes tantalum, and the inner layer 908 includes ruthenium. In one such embodiment, the outer layer 906 further includes nitrogen.

[0165] Referring to FIG. 9B, an interconnect line 920 in a dielectric layer 921 includes a conductive barrier material 922 and a conductive fill material 924. A conductive cap layer 930 is on a top of the conductive fill material 924. In one such embodiment, the conductive cap layer 930 is further on a top of the conductive barrier material 922, as is depicted. In another embodiment, the conductive cap layer 930 is not on a top of the conductive barrier material 922. In an embodiment, the conductive cap layer 930 consists essentially of cobalt, and the conductive fill material 924 consists essentially of copper.

[0166] Referring to FIG. 9C, an interconnect line 940 in a dielectric layer 941 includes a conductive barrier material 942 and a conductive fill material 944. The conductive barrier material 942 includes an outer layer 946 distal from the conductive fill material 944 and an inner layer 948 proximate to the conductive fill material 944. A conductive cap layer 950 is on a top of the conductive fill material 944. In one embodiment, the conductive cap layer 950 is only a top of the conductive fill material 944. In another embodiment, however, the conductive cap layer 950 is further on a top of the inner layer 948 of the conductive barrier material 942, i.e., at location 952. In one such embodiment, the conductive cap layer 950 is further on a top of the outer layer 946 of the conductive barrier material 942, i.e., at location 954.

[0167] In an embodiment, with reference to FIGS. 9B and 9C, a method of fabricating an integrated circuit structure includes forming an inter-layer dielectric (ILD) layer 921 or 941 above a substrate. A plurality of conductive interconnect lines 920 or 940 is formed in trenches in and spaced apart by the ILD layer, individual ones of the plurality of conductive interconnect lines 920 or 940 in a corresponding one of the trenches. The plurality of conductive interconnect lines is formed by first forming a conductive barrier material 922 or 924 on bottoms and sidewalls of the trenches, and then forming a conductive fill material 924 or 944 on the conductive barrier material 922 or 942, respectively, and filling the trenches, where the conductive barrier material 922 or 942 is along a bottom of and along sidewalls of the conductive fill material 930 or 950, respectively. The top of the conductive fill material 924 or 944 is then treated with a gas including oxygen and carbon. Subsequent to treating the top of the conductive fill material 924 or 944 with the gas including oxygen and carbon, a conductive cap layer 930 or 950 is formed on the top of the conductive fill material 924 or 944, respectively.

[0168] In one embodiment, treating the top of the conductive fill material 924 or 944 with the gas including oxygen and carbon includes treating the top of the conductive fill material 924 or 944 with carbon monoxide (CO). In one embodiment, the conductive fill material 924 or 944 includes copper, and forming the conductive cap layer 930 or 950 on the top of the conductive fill material 924 or 944 includes forming a layer including cobalt using chemical vapor deposition (CVD). In one embodiment, the conductive cap layer 930 or 950 is formed on the top of the conductive fill material 924 or 944, but not on a top of the conductive barrier material 922 or 924.

[0169] In one embodiment, forming the conductive barrier material 922 or 944 includes forming a first conductive layer on the bottoms and sidewalls of the trenches, the first conductive layer including tantalum. A first portion of the first conductive layer is first formed using atomic layer deposition (ALD) and then a second portion of the first conductive layer is then formed using physical vapor deposition (PVD). In one such embodiment, forming the conductive barrier material further includes forming a second conductive layer on the first conductive layer on the bottoms and sidewalls of the trenches, the second conductive layer including ruthenium, and the conductive fill material including copper. In one embodiment, the first conductive layer further includes nitrogen.

[0170] FIG. 10 illustrates a cross-sectional view of an integrated circuit structure having four metallization layers with a metal line composition and pitch above two metallization layers with a differing metal line composition and smaller pitch, in accordance with an embodiment of the present disclosure. It is to be appreciated that one or more of the interconnects or layers of interconnects described in association with FIG. 10 can be used in a process or included in a structure fabricated using split processing of integrated circuit layers with high accuracy bonding, such as is described in association with FIGS. 1A-1E.

[0171] Referring to FIG. 10, an integrated circuit structure 1000 includes a first plurality of conductive interconnect lines 1004 in and spaced apart by a first inter-layer dielectric (ILD) layer 1002 above a substrate 1001. Individual ones of the first plurality of conductive interconnect lines 1004 include a first conductive barrier material 1006 along sidewalls and a bottom of a first conductive fill material 1008. Individual ones of the first plurality of conductive interconnect lines 1004 are along a first direction 1098 (e.g., into and out of the page).

[0172] A second plurality of conductive interconnect lines 1014 is in and spaced apart by a second ILD layer 1012 above the first ILD layer 1002. Individual ones of the second plurality of conductive interconnect lines 1014 include the first conductive barrier material 1006 along sidewalls and a bottom of the first conductive fill material 1008. Individual ones of the second plurality of conductive interconnect lines 1014 are along a second direction 1099 orthogonal to the first direction 1098.

[0173] A third plurality of conductive interconnect lines 1024 is in and spaced apart by a third ILD layer 1022 above the second ILD layer 1012. Individual ones of the third plurality of conductive interconnect lines 1024 include a second conductive barrier material 1026 along sidewalls and a bottom of a second conductive fill material 1028. The second conductive fill material 1028 is different in composition from the first conductive fill material 1008. Individual ones of the third plurality of conductive interconnect lines 1024 are along the first direction 1098. In an embodiment, the second conductive barrier material 1026 is a single, nitrogen-free tantalum (Ta) barrier layer.

[0174] A fourth plurality of conductive interconnect lines 1034 is in and spaced apart by a fourth ILD layer 1032 above the third ILD layer 1022. Individual ones of the fourth plurality of conductive interconnect lines 1034 include the second conductive barrier material 1026 along sidewalls and a bottom of the second conductive fill material 1028. Individual ones of the fourth plurality of conductive interconnect lines 1034 are along the second direction 1099.

[0175] A fifth plurality of conductive interconnect lines 1044 is in and spaced apart by a fifth ILD layer 1042 above the fourth ILD layer 1032. Individual ones of the fifth plurality of conductive interconnect lines 1044 include the second conductive barrier material 1026 along sidewalls and a bottom of the second conductive fill material 1028. Individual ones of the fifth plurality of conductive interconnect lines 1044 are along the first direction 1098.

[0176] A sixth plurality of conductive interconnect lines 1054 is in and spaced apart by a sixth ILD layer 1052 above the fifth ILD layer. Individual ones of the sixth plurality of conductive interconnect lines 1054 include the second conductive barrier material 1026 along sidewalls and a bottom of the second conductive fill material 1028. Individual ones of the sixth plurality of conductive interconnect lines 1054 are along the second direction 1099.

[0177] In an embodiment, the second conductive fill material 1028 consists essentially of copper, and the first conductive fill material 1008 consists essentially of cobalt. In an embodiment, the first conductive fill material 1008 includes copper having a first concentration of a dopant impurity atom, and the second conductive fill material 1028 includes copper having a second concentration of the dopant impurity atom, the second concentration of the dopant impurity atom less than the first concentration of the dopant impurity atom.

[0178] In an embodiment, the first conductive barrier material 1006 is different in composition from the second conductive barrier material 1026. In another embodiment, the first conductive barrier material 1006 and the second conductive barrier material 1026 have the same composition.

[0179] In an embodiment, a first conductive via 1019 is on and electrically coupled to an individual one 1004A of the first plurality of conductive interconnect lines 1004. An individual one 1014A of the second plurality of conductive interconnect lines 1014 is on and electrically coupled to the first conductive via 1019.

[0180] A second conductive via 1029 is on and electrically coupled to an individual one 1014B of the second plurality of conductive interconnect lines 1014. An individual one 1024A of the third plurality of conductive interconnect lines 1024 is on and electrically coupled to the second conductive via 1029.

[0181] A third conductive via 1039 is on and electrically coupled to an individual one 1024B of the third plurality of conductive interconnect lines 1024. An individual one 1034A of the fourth plurality of conductive interconnect lines 1034 is on and electrically coupled to the third conductive via 1039.

[0182] A fourth conductive via 1049 is on and electrically coupled to an individual one 1034B of the fourth plurality of conductive interconnect lines 1034. An individual one 1044A of the fifth plurality of conductive interconnect lines 1044 is on and electrically coupled to the fourth conductive via 1049.

[0183] A fifth conductive via 1059 is on and electrically coupled to an individual one 1044B of the fifth plurality of conductive interconnect lines 1044. An individual one 1054A of the sixth plurality of conductive interconnect lines 1054 is on and electrically coupled to the fifth conductive via 1059.

[0184] In one embodiment, the first conductive via 1019 includes the first conductive barrier material 1006 along sidewalls and a bottom of the first conductive fill material 1008. The second 1029, third 1039, fourth 1049 and fifth 1059 conductive vias include the second conductive barrier material 1026 along sidewalls and a bottom of the second conductive fill material 1028.

[0185] In an embodiment, the first 1002, second 1012, third 1022, fourth 1032, fifth 1042 and sixth 1052 ILD layers are separated from one another by a corresponding etch-stop layer 1090 between adjacent ILD layers. In an embodiment, the first 1002, second 1012, third 1022, fourth 1032, fifth 1042 and sixth 1052 ILD layers include silicon, carbon and oxygen.

[0186] In an embodiment, individual ones of the first 1004 and second 1014 pluralities of conductive interconnect lines have a first width (W1). Individual ones of the third 1024, fourth 1034, fifth 1044 and sixth 1054 pluralities of conductive interconnect lines have a second width (W2) greater than the first width (W1).

[0187] In an aspect, one or more embodiments described herein are directed to approaches for building non-conductive spaces or interruptions between metals lines (referred to as line ends, plugs or cuts) and, in some embodiments, associated conductive vias. Conductive vias, by definition, are used to land on a previous layer metal pattern. In this vein, embodiments described herein enable a more robust interconnect fabrication scheme since alignment by lithography equipment is relied on to a lesser extent. Such an interconnect fabrication scheme can be used to relax constraints on alignment/exposures, can be used to improve electrical contact (e.g., by reducing via resistance), and can be used to reduce total process operations and processing time otherwise required for patterning such features using conventional approaches.

[0188] It is to be appreciated that dielectric plugs differing in composition from an ILD material in which they are housed may be included on only select metallization layers, such as in lower metallization layers. As an example, FIG. 11 illustrates a cross-sectional view of a stack of metallization layers including a conductive line plug at a lower metal line location, in accordance with an embodiment of the present disclosure. It is to be appreciated that one or more of the interconnects or layers of interconnects described in association with FIG. 11 can be used in a process or included in a structure fabricated using split processing of integrated circuit layers with high accuracy bonding, such as is described in association with FIGS. 1A-1E.

[0189] Referring to FIG. 11, an integrated circuit structure 1150 includes a first plurality of conductive interconnect lines 1156 in and spaced apart by a first inter-layer dielectric (ILD) layer 1154 above a substrate 1152. Individual ones of the first plurality of conductive interconnect lines 1156 have a continuity broken by one or more dielectric plugs 1158. In an embodiment, the one or more dielectric plugs 1158 include a material different than the ILD layer 1152. A second plurality of conductive interconnect lines 1166 is in and spaced apart by a second ILD layer 1164 above the first ILD layer 1154. In an embodiment, individual ones of the second plurality of conductive interconnect lines 1166 have a continuity broken by one or more portions 1168 of the second ILD layer 1164. It is to be appreciated, as depicted, that other metallization layers may be included in the integrated circuit structure 1150.

[0190] In one embodiment, the one or more dielectric plugs 1158 include a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In one embodiment, the first ILD layer 1154 and the second ILD layer 1164 (and, hence, the one or more portions 1168 of the second ILD layer 1164) include a carbon-doped silicon oxide material.

[0191] In one embodiment, individual ones of the first plurality of conductive interconnect lines 1156 include a first conductive barrier liner 1156A and a first conductive fill material 1156B. Individual ones of the second plurality of conductive interconnect lines 1166 include a second conductive barrier liner 1166A and a second conductive fill material 1166B. In one such embodiment, the first conductive fill material 1156B is different in composition from the second conductive fill material 1166B. In a particular such embodiment, the first conductive fill material 1156B includes cobalt, and the second conductive fill material 1166B includes copper.

[0192] In one embodiment, the first plurality of conductive interconnect lines 1156 has a first pitch (P1, as shown in like-layer 1170). The second plurality of conductive interconnect lines 1166 has a second pitch (P2, as shown in like-layer 1180). The second pitch (P2) is greater than the first pitch (P1). In one embodiment, individual ones of the first plurality of conductive interconnect lines 1156 have a first width (W1, as shown in like-layer 1170). Individual ones of the second plurality of conductive interconnect lines 1166 have a second width (W2, as shown in like-layer 1180). The second width (W2) is greater than the first width (W1).

[0193] It is to be appreciated that the layers and materials described above in association with back-end-of-line (BEOL) structures and processing may be formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials, such as substrates including germanium, carbon, or group III-V materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structures depicted may be fabricated on underlying lower level interconnect layers.

[0194] Although the preceding methods of fabricating a metallization layer, or portions of a metallization layer, of a BEOL metallization layer are described in detail with respect to select operations, it is to be appreciated that additional or intermediate operations for fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other associated action with microelectronic component fabrication. Also, it is to be appreciated that the process operations described for the preceding process flows may be practiced in alternative sequences, not every operation need be performed or additional process operations may be performed or both.

[0195] In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO.sub.2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0196] In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

[0197] In an embodiment, as is also used throughout the present description, hardmask materials are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hardmask layers known in the arts may be used depending upon the particular implementation. The hardmask layers maybe formed by CVD, PVD, or by other deposition methods.

[0198] In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion lithography (i193), extreme ultra-violet (EUV) lithography or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a tri-layer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

[0199] Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

[0200] FIG. 12 illustrates a computing device 1200 in accordance with one implementation of the disclosure. The computing device 1200 houses a board 1202. The board 1202 may include a number of components, including but not limited to a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some implementations the at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In further implementations, the communication chip 1206 is part of the processor 1204.

[0201] Depending on its applications, computing device 1200 may include other components that may or may not be physically and electrically coupled to the board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0202] The communication chip 1206 enables wireless communications for the transfer of data to and from the computing device 1200. The term wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1206 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1200 may include a plurality of communication chips 1206. For instance, a first communication chip 1206 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1206 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0203] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures built in accordance with implementations of the disclosure. The term processor may refer to any device or portion of a device that processes electronic data from registers or memory to transform that electronic data, or both, into other electronic data that may be stored in registers or memory, or both.

[0204] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip is built in accordance with implementations of the disclosure.

[0205] In further implementations, another component housed within the computing device 1200 may contain an integrated circuit die built in accordance with implementations of embodiments of the disclosure.

[0206] In various embodiments, the computing device 1200 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1200 may be any other electronic device that processes data.

[0207] FIG. 13 illustrates an interposer 1300 that includes one or more embodiments of the disclosure. The interposer 1300 is an intervening substrate used to bridge a first substrate 1302 to a second substrate 1304. The first substrate 1302 may be, for instance, an integrated circuit die. The second substrate 1304 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1300 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306 that can subsequently be coupled to the second substrate 1304. In some embodiments, the first and second substrates 1302/1304 are attached to opposing sides of the interposer 1300. In other embodiments, the first and second substrates 1302/1304 are attached to the same side of the interposer 1300. And in further embodiments, three or more substrates are interconnected by way of the interposer 1300.

[0208] The interposer 1300 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 1300 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0209] The interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1312. The interposer 1300 may further include embedded devices 1314, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1300. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1300 or in the fabrication of components included in the interposer 1300.

[0210] FIG. 14 is an isometric view of a mobile computing platform 1400 employing an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0211] The mobile computing platform 1400 may be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform 1400 may be any of a tablet, a smart phone, laptop computer, etc. and includes a display screen 1405 which in the exemplary embodiment is a touchscreen (capacitive, inductive, resistive, etc.), a chip-level (SoC) or package-level integrated system 1410, and a battery 1413. As illustrated, the greater the level of integration in the system 1410 enabled by higher transistor packing density, the greater the portion of the mobile computing platform 1400 that may be occupied by the battery 1413 or non-volatile storage, such as a solid state drive, or the greater the transistor gate count for improved platform functionality. Similarly, the greater the carrier mobility of each transistor in the system 1410, the greater the functionality. As such, techniques described herein may enable performance and form factor improvements in the mobile computing platform 1400.

[0212] The integrated system 1410 is further illustrated in the expanded view 1420. In the exemplary embodiment, packaged device 1477 includes at least one memory chip (e.g., RAM), or at least one processor chip (e.g., a multi-core microprocessor and/or graphics processor) fabricated according to one or more processes described herein or including one or more features described herein. The packaged device 1477 is further coupled to the board 1460 along with one or more of a power management integrated circuit (PMIC) 1415, RF (wireless) integrated circuit (RFIC) 1425 including a wideband RF (wireless) transmitter and/or receiver (e.g., including a digital baseband and an analog front end module further includes a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller thereof 1411. Functionally, the PMIC 1415 performs battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to the battery 1413 and with an output providing a current supply to all the other functional modules. As further illustrated, in the exemplary embodiment, the RFIC 1425 has an output coupled to an antenna to provide to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of the packaged device 1477 or within a single IC (SoC) coupled to the package substrate of the packaged device 1477.

[0213] In another aspect, semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support larger circuit density. Furthermore, the demand for higher performance devices results in a need for an improved semiconductor package that enables a thin packaging profile and low overall warpage compatible with subsequent assembly processing.

[0214] In an embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount a die to a ceramic or organic package substrate. In particular, C4 solder ball connections can be implemented to provide flip chip interconnections between semiconductor devices and substrates. A flip chip or Controlled Collapse Chip Connection (C4) is a type of mounting used for semiconductor devices, such as integrated circuit (IC) chips, MEMS or components, which utilizes solder bumps instead of wire bonds. The solder bumps are deposited on the C4 pads, located on the top side of the substrate package. In order to mount the semiconductor device to the substrate, it is flipped over with the active side facing down on the mounting area. The solder bumps are used to connect the semiconductor device directly to the substrate.

[0215] FIG. 15 illustrates a cross-sectional view of a flip-chip mounted die, in accordance with an embodiment of the present disclosure.

[0216] Referring to FIG. 15, an apparatus 1500 includes a die 1502 such as an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure. The die 1502 includes metallized pads 1504 thereon. A package substrate 1506, such as a ceramic or organic substrate, includes connections 1508 thereon. The die 1502 and package substrate 1506 are electrically connected by solder balls 1510 coupled to the metallized pads 1504 and the connections 1508. An underfill material 1512 surrounds the solder balls 1510.

[0217] Processing a flip chip may be similar to conventional IC fabrication, with a few additional operations. Near the end of the manufacturing process, the attachment pads are metalized to make them more receptive to solder. This typically consists of several treatments. A small dot of solder is then deposited on each metalized pad. The chips are then cut out of the wafer as normal. To attach the flip chip into a circuit, the chip is inverted to bring the solder dots down onto connectors on the underlying electronics or circuit board. The solder is then re-melted to produce an electrical connection, typically using an ultrasonic or alternatively reflow solder process. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases an electrically-insulating adhesive is then underfilled to provide a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0218] In other embodiments, newer packaging and die-to-die interconnect approaches, such as through silicon via (TSV) and silicon interposer, are implemented to fabricate high performance Multi-Chip Module (MCM) and System in Package (SiP) incorporating an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0219] Thus, split processing of integrated circuit layers with high accuracy bonding has been disclosed.

[0220] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims.

[0221] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of the present disclosure.

[0222] The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of the present application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

[0223] Various embodiments or aspects of the disclosure are described herein. In some implementations, the different embodiments are practiced separately. However, embodiments are not limited to embodiments being practiced in isolation. For example, two or more different embodiments can be combined together in order to be practiced as a single device, process, structure, or the like. The entirety of various embodiments can be combined together in some instances. In other instances, portions of a first embodiment can be combined with portions of one or more different embodiments. For example, a portion of a first embodiment can be combined with a portion of a second embodiment, or a portion of a first embodiment can be combined with a portion of a second embodiment and a portion of a third embodiment., etc. The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.

[0224] Example embodiment 1: An integrated circuit structure includes a front-end-of-line (FEOL) stack having an uppermost surface including first conductive features and first dielectric features. A back-end-of-line (BEOL) stack is above the FEOL stack. The BEOL stack has a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the uppermost surface of the FEOL stack, respectively. The second conductive features are laterally offset from the corresponding first conductive features.

[0225] Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein the first and second conductive features include copper, and the first and second dielectric features include silicon and oxygen.

[0226] Example embodiment 3: The integrated circuit structure of example embodiment 1 or 2, wherein the FEOL stack includes gate-all-around-based devices.

[0227] Example embodiment 4: The integrated circuit structure of example embodiment 1 or 2, wherein the FEOL stack includes fin-based devices.

[0228] Example embodiment 5: The integrated circuit structure of example embodiment 1, 2, 3 or 4, further including a backside stack having an uppermost surface in contact with a bottommost surface of the FEOL stack.

[0229] Example embodiment 6: An integrated circuit structure includes a front-end-of-line (FEOL) stack having a bottommost surface including first conductive features and first dielectric features. A backside stack is below the FEOL stack. The backside stack has an uppermost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the bottommost surface of the FEOL stack, respectively. The second conductive features are laterally offset from the corresponding first conductive features.

[0230] Example embodiment 7: The integrated circuit structure of example embodiment 6, wherein the first and second conductive features include copper, and the first and second dielectric features include silicon and oxygen.

[0231] Example embodiment 8: The integrated circuit structure of example embodiment 6 or 7, wherein the FEOL stack includes gate-all-around-based devices.

[0232] Example embodiment 9: The integrated circuit structure of example embodiment 6 or 7, wherein the FEOL stack includes fin-based devices.

[0233] Example embodiment 10: The integrated circuit structure of example embodiment 6, 7, 8 or 9, further including a back-end-of-line (BEOL) stack having a bottommost surface in contact with an uppermost surface of the FEOL stack.

[0234] Example embodiment 11: A computing device includes a board, and a component coupled to the board. The component includes an integrated circuit structure including a front-end-of-line (FEOL) stack having a surface including first conductive features and first dielectric features. The computing device includes a back-end-of-line (BEOL) stack above the FEOL stack, where the BEOL stack has a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the surface of the FEOL stack, respectively, and where the second conductive features are laterally offset from the corresponding first conductive features, or the computing device includes a backside stack below the FEOL stack, where the backside stack has an uppermost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the surface of the FEOL stack, respectively, and where the second conductive features are laterally offset from the corresponding first conductive features.

[0235] Example embodiment 12: The computing device of example embodiment 11, including the BEOL stack above the FEOL stack.

[0236] Example embodiment 13: The computing device of example embodiment 11, including the backside stack below the FEOL stack.

[0237] Example embodiment 14: The computing device of example embodiment 11, 12 or 13, further including a memory coupled to the board.

[0238] Example embodiment 15: The computing device of example embodiment 11, 12, 13 or 14, further including a communication chip coupled to the board.

[0239] Example embodiment 16: The computing device of example embodiment 11, 12, 13, 14 or 15, further including a battery coupled to the board.

[0240] Example embodiment 17: The computing device of example embodiment 11, 12, 13, 14, 15 or 16, further including a camera coupled to the board.

[0241] Example embodiment 18: The computing device of example embodiment 11, 12, 13, 14, 15, 16 or 17, further including a display coupled to the board.

[0242] Example embodiment 19: The computing device of example embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0243] Example embodiment 20: The computing device of example embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.