A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.

There is provided a semiconductor device 1, comprising: a housing comprising a housing electrode 4; and at least one semiconductor chip 20 arranged within the housing; wherein the housing electrode 4 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between an interior and an exterior of the housing exceeds a threshold differential pressure or a temperature at the deformable portion exceeds a threshold temperature, so as to transform the housing from a hermetically sealed housing to an open housing in fluid communication with the exterior.

A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

A structure includes a combinational semiconductor die, an interposer, and solder bumps coupled between the combinational semiconductor die and the interposer. The combinational semiconductor die includes a first unit region and a second unit region over a semiconductor substrate. The first unit region abuts the second unit region. The first unit region includes a first device portion and a first dummy portion. The second unit region includes a second device portion and a second dummy portion The first dummy portion includes a first conductive feature and the second dummy portion includes a second conductive feature in physical contact with the first conductive feature.

The invention provides a semiconductor structure including alignment marks, which comprises a substrate defining a peripheral region, a first gate structure located in the peripheral region on the substrate, wherein the first gate structure has a left boundary and a right boundary, a dielectric layer covers the first gate structure in the peripheral region, a first left slot contact groove located in the dielectric layer on the left side of the first gate structure, a first right slot contact groove located in the dielectric layer on the right side of the first gate structure, and a first gate opening exposing a left boundary and a right boundary of the first gate structure, a boundary of the first left slot contact groove and a boundary of the first right slot contact groove.

A semiconductor structure includes a circuit region, a seal ring region and at least one alignment mark. The seal ring region surrounds the circuit region and includes a seal ring corner region. The seal ring is disposed in the seal ring region, and includes a corner seal ring portion in the seal ring corner region. The corner seal ring portion divides the seal ring corner region into a plurality of sub-regions, and the at least one alignment mark is disposed in at least one of the sub-regions of the seal ring corner region.

Bonded die structures and methods of fabricating bonded die structures including improved positioning of the dies used to form the structures. Improved positioning may be achieved by providing non-linear alignment features around the periphery of the dies that may facilitate accurate positioning of the dies with respect to one or more alignment marks on the target structures on which the dies are placed. The non-linear alignment features may include features formed in the peripheral edges of the dies, such as indent portions extending inwardly from the peripheral edges of the dies and/or outward bulge portions extending outwardly from the peripheral edges of the dies. Alternatively, or in addition, the non-linear alignment features may be features formed in a seal ring structure of the dies. The non-linear alignment features may improve the accuracy of the positioning of the dies relative to alignment mark(s) on the target structures using optical detection systems.

A method of manufacturing a semiconductor device includes cutting a substrate structure along a scribe lane to separate a plurality of semiconductor devices from the substrate structure. The substrate structure includes a plurality of device regions and the scribe lane separates the plurality of device regions. Each of the plurality of device regions includes a first side and a second side opposite the first side. Each of the plurality of device regions includes bonding pads arranged along the first side, and bonding pads are absent on a region adjacent to the second side. The plurality of device regions are arranged such that the first side and the second side of adjacent device regions face each other and the scribe lane is therebetween in the substrate structure. The substrate structure further includes metal patterns arranged closer to the second side than to the first side in the scribe lane.

The invention concerns a method of manufacturing an assembly of electronic components on a front surface of a semiconductor substrate comprising a plurality of field areas, each field area comprising at least one field and each field comprising at least one electronic component, the method comprising a plurality of photolithography steps to form a stack of layers forming each electronic component, each photolithography step defining a mask level and comprising the application of a mask successively on each field in photolithography equipment, the positioning of said mask on each field being performed relative to a reference mask level, one of the masks being designated as identification mask. The manufacturing method is remarkable in that: at the photolithography step defining a mask level associated with the identification mask, said mask is positioned with a predetermined offset with respect to the reference mask level, the offset being different for each field area, the electronic component(s) of a field area have an identification element appearing as a predetermined offset between a pattern defined at the reference mask level and a pattern defined at the identification mask level.